Memory Layout Design Engineer

Broadcom
India
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["Communicate effectively","Lead and train","Self-reliant","Independently and collaboratively","Manage projects"]

Design and deliver high-quality memory layouts for advanced CMOS process nodes, applying layout guidelines and new process rules. Own start-to-end deliverables including scheduling, timelines, and layout floor-planning, spanning digital memory layout and physical verification. Use Cadence (Virtuoso tools) plus verification flows (CALIBRE, Hercules) and support chip integration with floor-planning, hierarchy, and memory topology. Collaborate with the SOC/library team and lead reviews or junior engineers.

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FursaFursa
Broadcom
Broadcom
3 days ago

Memory Layout Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 minutes agoStatus: Live
Reposted: similar role first listed 2 weeks ago

Job Summary

Design and deliver high-quality memory layouts for advanced CMOS process nodes, applying layout guidelines and new process rules. Own start-to-end deliverables including scheduling, timelines, and layout floor-planning, spanning digital memory layout and physical verification. Use Cadence (Virtuoso tools) plus verification flows (CALIBRE, Hercules) and support chip integration with floor-planning, hierarchy, and memory topology. Collaborate with the SOC/library team and lead reviews or junior engineers.
Location: India
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Understand and apply layout guidelines, new process rules, and technical requirements to ensure layout quality.
  • •Manage scheduling, timelines, and layout floor-planning.
  • •Own start-to-end deliverables with quality within the planned schedule.
  • •Adapt quickly to new methodologies and remain open to new ideas while communicating with the SOC/library team.
  • •Lead new technology reviews to document layout methodologies, flows, and guidelines.

Key Requirements

  • •Minimum 3 years of experience with strong layout knowledge.
  • •Bachelor's degree required.
  • •Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools CALIBRE & Hercules).
  • •Strong layout knowledge in submicron processes (e.g., A14, 2nm, 3nm, 5nm, 7nm).
  • •Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.
Experience:3+ yearsSemiconductorCMOS
Education:Bachelor's
Skills:Communicate effectivelyLead and trainSelf-reliantIndependently and collaborativelyManage projects
Tech Stack:Cadence Virtuoso LayoutLayout XLCadence Schematic CaptureCALIBREHerculesLVSDRCERCAntennaElectroMigrationCMOSVIRTUOSO XLVXLEXLFloor-planningHierarchy layoutChip integrationSKILLAutomationMemory compilers

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn