Senior System Level Test Engineer - LPU
Santa Clara
Workplace: OnsiteFull timeFunction: QA, Test & Release EngineeringExperience: 12+ yearsEducation: mastersSkills: ["Collaboration","Problem-solving","Cross-functional teamwork"]Lead the design, automation, and validation of System Level Tests (SLT) for high power, high speed SOCs for HVM, collaborating with system architecture, chip design and validation teams to deliver production-ready SLT solutions. Drive custom SLT development to optimize performance and test coverage, while overseeing hardware integration and test quality across NPI, HVM and RMA processes.
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