Senior Design Verification Engineer - Interconnect IP

NVIDIA
Shanghai
Full timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: mastersSkills: ["Debugging","Analytical skills","Communication skills","Cross-team coordination","Teamwork"]

Verify the ASIC design, architecture, and micro-architecture of the GPU memory subsystem unit using advanced verification methodologies. Own the verification scope, build verification infrastructure, and create test plans, tests, monitors, checkers, and scoreboards using coverage-driven verification. Drive functional coverage closure, including performance and deadlock verification, and collaborate with architects, designers, and pre/post-silicon verification teams to ensure correctness.

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FursaFursa
NVIDIA
NVIDIA
14 hours ago

Senior Design Verification Engineer - Interconnect IP

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Source: Company careers pageValidated by: Fursa AI
Last checked: 14 hours agoStatus: Live

Job Summary

Verify the ASIC design, architecture, and micro-architecture of the GPU memory subsystem unit using advanced verification methodologies. Own the verification scope, build verification infrastructure, and create test plans, tests, monitors, checkers, and scoreboards using coverage-driven verification. Drive functional coverage closure, including performance and deadlock verification, and collaborate with architects, designers, and pre/post-silicon verification teams to ensure correctness.
Location: Shanghai
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Verify the ASIC design, architecture, and micro-architecture of the GPU memory subsystem unit using advanced verification methodologies.
  • •Define verification scope, develop verification infrastructure, and ensure design correctness through comprehensive verification.
  • •Create test plans, tests, and verification infrastructure for complex IPs and sub-systems.
  • •Build reusable bus functional models, monitors, checkers, and scoreboards using coverage-driven verification.
  • •Execute performance and deadlock verification and drive functional coverage closure in collaboration with relevant teams.

Key Requirements

  • •Master's degree (or equivalent experience) in Electrical/Computer Engineering or a related field.
  • •5+ years of ASIC design verification experience on complex IPs, units, or sub-systems.
  • •Deep understanding of verification methodologies and languages including Verilog, SystemVerilog, and UVM.
  • •Hands-on experience across the full verification flow: testplan, tests, coverage model, testbench, and BFM modeling.
  • •Experience with random stimulus plus functional coverage and assertion-based verification methodologies.
Experience:5+ yearsASICGPUSemiconductorInterconnect IPMemory subsystem
Education:Master's in Electrical/Computer Engineering
Skills:DebuggingAnalytical skillsCommunication skillsCross-team coordinationTeamwork
Languages:English
Tech Stack:ASICGPUVerilogSystemVerilogUVMCoverage-driven verificationFunctional coverageAssertion-based verificationTestbenchBFM modelingMonitorsCheckersScoreboardsSimulation and debug

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
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