Senior Cell Modeling and Verification Engineer
United States
Workplace: HybridFull timeUSD 136,000 - 218,500 annuallyFunction: Solutions Engineering & Sales EngineeringExperience: 3+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","Python","Perl","RTL","DFT"]Senior ASIC-focused engineer responsible for developing behavioral models and verification for custom mixed-signal design cells used across NVIDIA products. Collaborates on library build, cell integration, ASIC verification and DFT simulations, delivering high-performance RTL and verified designs using Verilog/SystemVerilog, Python or Perl. Strong digital design fundamentals and hands-on RTL waveform debugging are essential to meet design targets.
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