DFT Methodology Engineer

Own and drive Design-for-Test (DFT) methodology for next-generation semiconductor products. Collaborate cross-functionally to implement test access mechanisms (including I1149.1, I1500, I1687, and 1838), develop and deploy DFT approaches, and support verification through pattern generation and post-silicon validation. Work on silicon debug and ATE bring-up, and mentor junior engineers on DFT test design trade-offs across cost and quality.