DFT Methodology Engineer

NVIDIA
United States
Workplace: OnsiteFull timeUSD 168,000 - 310,500 annuallyFunction: QA, Test & Release EngineeringExperience: 10+ yearsEducation: mastersSkills: ["Analytical skills","Interpersonal skills","Mentoring","Curiosity","Cross-functional collaboration"]

Own and drive Design-for-Test (DFT) methodology for next-generation semiconductor products. Collaborate cross-functionally to implement test access mechanisms (including I1149.1, I1500, I1687, and 1838), develop and deploy DFT approaches, and support verification through pattern generation and post-silicon validation. Work on silicon debug and ATE bring-up, and mentor junior engineers on DFT test design trade-offs across cost and quality.

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FursaFursa
NVIDIA
NVIDIA
2 months ago

DFT Methodology Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 16 hours agoStatus: Live

Job Summary

Own and drive Design-for-Test (DFT) methodology for next-generation semiconductor products. Collaborate cross-functionally to implement test access mechanisms (including I1149.1, I1500, I1687, and 1838), develop and deploy DFT approaches, and support verification through pattern generation and post-silicon validation. Work on silicon debug and ATE bring-up, and mentor junior engineers on DFT test design trade-offs across cost and quality.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: QA, Test & Release Engineering
Seniority: Mid level

Key Responsibilities

  • •Partner with cross-functional teams to implement state-of-the-art DFT designs in test access mechanisms and related security methodology.
  • •Architect, develop, and deploy DFT methodologies for next-generation products, including RTL, verification, and pattern generation.
  • •Collaborate with teams across timing, physical design, software, bring-up, and production to deliver test-ready designs.
  • •Support silicon debug and post-silicon validation, including ATE bring-up and failure processing.
  • •Mentor junior engineers on DFT test design trade-offs, balancing cost and quality.

Pay and Benefits

Salary: USD 168,000 - 310,500 annually
Equity and Bonus:Equity

Key Requirements

  • •Master’s degree (or equivalent experience) in Electrical Engineering (or related) with proven DFT experience.
  • •10+ years of hands-on experience in SoC architecture, RTL design, and verification.
  • •Excellent analytical skills validating test patterns and logic on complex, multi-million gate designs using vendor tools.
  • •Strong understanding of DFT methodologies and cross-functional areas such as RTL & clocks design, STA, place-and-route, and power for making trade-offs.
  • •Experience with silicon debug and bring-up on the ATE, including pattern formats, failure processing, and test program development.
Experience:10+ yearsSemiconductorsSoCRTL designDFTSilicon debug
Education:Master's in Electrical Engineering
Skills:Analytical skillsInterpersonal skillsMentoringCuriosityCross-functional collaboration
Tech Stack:DFTDesign-for-TestI1149.1I1500I16871838Memory BISTScanMemory dumpDFX security methodologyRTL designVerificationPattern generationTimingPhysical designBringupSoC architectureVendor toolsRTL & clocks designSTA

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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Glassdoor: 4.3
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