5 months ago

Principal Application Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 4 hours agoStatus: Live

Job Summary

Lead and execute physical design for ASICs, including floorplanning, power grid design, place-and-route, clock tree synthesis, timing closure, signoffs (power/signal integrity, DRC/LVS/antenna, EM/IR), and P&R verification on low-power and high-speed designs at advanced nodes. Collaborate with RTL teams to ensure successful tapeouts and drive next-generation design flows.

Location: Shanghai

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Key Responsibilities

•Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
•Work on varieties of challenging designs, e.g. low power and high speed designs at the latest technology nodes.
•Participate in or lead next generation physical design, methodology and flow development.
•Work closely with RTL design team to ensure successful tapeouts.

Key Requirements

•BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verification.
•Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues.
•Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR‑Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
•Able to assume responsibility for a variety of technical tasks and to work independently.
•Hands-on at all levels of design, with the ability to verify, test, and characterize own designs; good English communication skills.

Experience:3+ yearsASICHardwareSemiconductors

Education:Bachelor's in Electrical Engineering / Computer Science

Skills:VerilogDfTStatic timing analysisClock tree synthesisPlace and routeFlow developmentTapeout

Languages:English

Tech Stack:ASIC design flowFloorplanningPower grid designPlace and routeClock tree synthesisTiming closureDRCLVSAntennaEM/IR signoffDFMP&RLow power designDFTEM/IR analysis

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

5 months ago

Principal Application Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 4 hours agoStatus: Live

Job Summary

Location: Shanghai

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Key Responsibilities

•Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
•Work on varieties of challenging designs, e.g. low power and high speed designs at the latest technology nodes.
•Participate in or lead next generation physical design, methodology and flow development.
•Work closely with RTL design team to ensure successful tapeouts.

Key Requirements

•BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verification.
•Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues.
•Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR‑Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
•Able to assume responsibility for a variety of technical tasks and to work independently.
•Hands-on at all levels of design, with the ability to verify, test, and characterize own designs; good English communication skills.

Experience:3+ yearsASICHardwareSemiconductors

Education:Bachelor's in Electrical Engineering / Computer Science

Skills:VerilogDfTStatic timing analysisClock tree synthesisPlace and routeFlow developmentTapeout

Languages:English

Tech Stack:ASIC design flowFloorplanningPower grid designPlace and routeClock tree synthesisTiming closureDRCLVSAntennaEM/IR signoffDFMP&RLow power designDFTEM/IR analysis

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor