ASIC Physical Design Intern - 2027

NVIDIA
China
Workplace: OnsiteInternshipFunction: Design (Product/UX/UI/Visual)Skills: ["Self-driven","Good learning ability","Teamwork","Communication"]

Work on ASIC physical design from RTL freeze through tape-out, supporting synthesis, formal verification, constraint definition, and timing closure/sign-off. Collaborate across teams on chip integration, netlist generation, partitioning, and floorplanning. Create and validate constraints, analyze and resolve function timing issues, and partner with PR engineers for full-chip timing closure while helping develop and automate timing-closure flows from pre- to post-layout.

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FursaFursa
NVIDIA
NVIDIA
2 weeks ago

ASIC Physical Design Intern - 2027

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live
Reposted: similar role first listed 1 day ago

Job Summary

Work on ASIC physical design from RTL freeze through tape-out, supporting synthesis, formal verification, constraint definition, and timing closure/sign-off. Collaborate across teams on chip integration, netlist generation, partitioning, and floorplanning. Create and validate constraints, analyze and resolve function timing issues, and partner with PR engineers for full-chip timing closure while helping develop and automate timing-closure flows from pre- to post-layout.
Location: China
Workplace: Onsite
Employment Type: Internship
Job Function: Design (Product/UX/UI/Visual)
Seniority: Intern level

Key Responsibilities

  • •Support chip integration and netlist generation, partnering with teams on chip partitioning and floorplan implementation
  • •Perform synthesis, RTL/netlist quality checks, formal verification, and function ECO creation
  • •Create and validate constraints and timing budgets; analyze and help resolve function timing issues for special timing closure (IO, test, clock, async, etc.)
  • •Collaborate with PR engineers to achieve full-chip timing closure
  • •Develop and improve timing-closure flow from frontend (pre-layout) to backend (post-layout), including flow automation and methodology work

Key Requirements

  • •Currently pursuing a Master’s or PhD degree in a relevant or related field
  • •Strong knowledge in IC design
  • •Experience or strong interest in IC backend implementation
  • •Self-driven with good learning ability and teamwork
  • •Excellent communication skills; proficient in English reading and writing
Skills:Self-drivenGood learning abilityTeamworkCommunication
Languages:English
Tech Stack:RTLTape outSynthesisFormal verificationConstraintsTiming closureNetlistFloorplanChip partitioningSynopsys DCSynopsys PTSynopsys FormalityCadence RC CompilerCadence LECPythonTCLEDA

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
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