PRINCIPAL ENGINEER, DDEG DESIGN METHOD
Hyderabad, Telangana, India
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Communication","Debugging","Teamwork","Analytical thinking"]Own verification of sophisticated, full-chip gate-level custom DRAM designs using advanced low-power and power-management methods. Accelerate verification cycle time with AI-based tools and automation, improve debug efficiency, and validate AI outputs against specs, simulations, waveforms, assertions, and coverage. Simulate and debug pre-silicon designs, develop SV/UVM testbenches and stimulus to boost coverage, and build/maintain test benches, vectors, and regressions. Collaborate globally on new verification flows and environments.
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