Sr. Memory Layout Design Engineer

Broadcom
India
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Communicate effectively","Adapt to new methodologies","Work independently and collaboratively","Lead and train junior engineers","Project management"]

Own memory layout design and physical verification for advanced CMOS processes, applying layout guidelines and new process rules to deliver high-quality results on schedule. Handle end-to-end deliverables including floor-planning, hierarchy and chip integration, and scripting/automation to improve flows. Collaborate with the SOC/library team, lead technology reviews, and support/mentor junior engineers while working with Cadence and verification tools like CALIBRE and Hercules.

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FursaFursa
Broadcom
Broadcom
3 days ago

Sr. Memory Layout Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 13 minutes agoStatus: Live
Reposted: similar role first listed 3 weeks ago

Job Summary

Own memory layout design and physical verification for advanced CMOS processes, applying layout guidelines and new process rules to deliver high-quality results on schedule. Handle end-to-end deliverables including floor-planning, hierarchy and chip integration, and scripting/automation to improve flows. Collaborate with the SOC/library team, lead technology reviews, and support/mentor junior engineers while working with Cadence and verification tools like CALIBRE and Hercules.
Location: India
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Understand and apply layout guidelines, new process rules, and technical requirements to produce good-quality layout.
  • •Manage scheduling, timelines, and layout floor-planning while delivering start-to-end results within the planned schedule.
  • •Deliver strong memory layout design and physical verification using LVS/DRC/ERC/Antenna/ElectroMigration and CMOS process understanding.
  • •Work on layout scripting and automation, and adapt quickly to new methodologies while communicating with the SOC/library team.
  • •Plan signal/power based on layout guidelines, help lead technology reviews and document methodologies/flows, and support/mentor junior engineers.

Key Requirements

  • •Minimum 8 years of experience with strong layout knowledge.
  • •Bachelor's degree required.
  • •Proficiency with Cadence layout tools (Virtuoso layout/VXL/EXL) including schematic capture and verification tools such as CALIBRE & Hercules.
  • •Strong digital memory layout experience (Standard cell, Memory, I/O) in submicron CMOS processes (e.g., 7nm, 5nm, 3nm, 2nm).
  • •Experience with memory physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) and the ability to support layout scripting/automation (SKILL/programming).
Experience:8+ yearsCMOSSubmicron processesMemory layoutPhysical verification
Education:Bachelor's
Skills:Communicate effectivelyAdapt to new methodologiesWork independently and collaborativelyLead and train junior engineersProject management
Tech Stack:CadenceVirtuoso layoutVirtuoso XLVXLEXLCadence schematic captureCALIBREHerculesLVSDRCERCAntennaElectroMigrationFloor-planningHierarchy layoutChip integrationSKILLScriptingAutomationMemory compilers

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn