3 months ago

Senior ASIC Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 hours agoStatus: Live

Job Summary

Senior ASIC Verification Engineer to verify design and implementation of leading SoCs and GPUs, driving verification infrastructure, DV strategies, and test planning for memory subsystems while collaborating with ASIC designers and architects to ensure bug-free first silicon across AI/compute platforms.

Location: Santa Clara

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Verify the design, architecture and micro-architecture using advanced verification methodologies.
•Define verification scope and drive the development of verification infrastructure, DV strategies and test plans for memory subsystem units.
•Collaborate with ASIC designers and architects in feature and micro-architecture discussions.
•Develop and maintain scalable verification environments and test plans to cover multiple chip generations.
•Deliver high-quality silicon by identifying and debugging issues early in the verification process.

Pay and Benefits

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent)
•4+ years of experience verifying a complex unit from start to tapeout for 1-2 generations of chips
•Knowledge of verification techniques such as constrained random sequences, scoreboard and functional coverage
•Experience developing scalable code using Object Oriented Programming principles and proficiency in SystemVerilog/ UVM
•Familiarity with memory subsystem concepts (memory consistency models, arbitration policies, interface protocols, on-chip interconnect)

Experience:4+ yearsSemiconductorsHardwareAIGPUSoC

Education:Bachelor's

Skills:SystemVerilogUVMConstrained randomMemory subsystem

Tech Stack:SystemVerilogUVMConstrained randomMemory subsystems

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

3 months ago

Senior ASIC Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 hours agoStatus: Live

Job Summary

Location: Santa Clara

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Verify the design, architecture and micro-architecture using advanced verification methodologies.
•Define verification scope and drive the development of verification infrastructure, DV strategies and test plans for memory subsystem units.
•Collaborate with ASIC designers and architects in feature and micro-architecture discussions.
•Develop and maintain scalable verification environments and test plans to cover multiple chip generations.
•Deliver high-quality silicon by identifying and debugging issues early in the verification process.

Pay and Benefits

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent)
•4+ years of experience verifying a complex unit from start to tapeout for 1-2 generations of chips
•Knowledge of verification techniques such as constrained random sequences, scoreboard and functional coverage
•Experience developing scalable code using Object Oriented Programming principles and proficiency in SystemVerilog/ UVM
•Familiarity with memory subsystem concepts (memory consistency models, arbitration policies, interface protocols, on-chip interconnect)

Experience:4+ yearsSemiconductorsHardwareAIGPUSoC

Education:Bachelor's

Skills:SystemVerilogUVMConstrained randomMemory subsystem

Tech Stack:SystemVerilogUVMConstrained randomMemory subsystems

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor