Director, Physical Design (Silicon One)

Cisco
San Jose
Workplace: HybridFull timeUSD 250,600 - 362,600 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 15+ yearsEducation: bachelorsSkills: ["Leadership","Cross-functional collaboration","Risk communication","Self-motivation"]

Lead and manage SoC physical design execution for Cisco Silicon One, driving schedule execution, floor-plan and interconnect optimization, and PPA goals across advanced process nodes. Provide technical leadership for physical design implementation and world-class teams spanning physical design, circuit design, DFT, and integration. Partner globally across RTL, NPI, packaging, and architecture teams, build automation utilities, and run rigorous design reviews including EMIR analysis and timing signoff closure.

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Cisco
Cisco
1 day ago

Director, Physical Design (Silicon One)

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Job Summary

Lead and manage SoC physical design execution for Cisco Silicon One, driving schedule execution, floor-plan and interconnect optimization, and PPA goals across advanced process nodes. Provide technical leadership for physical design implementation and world-class teams spanning physical design, circuit design, DFT, and integration. Partner globally across RTL, NPI, packaging, and architecture teams, build automation utilities, and run rigorous design reviews including EMIR analysis and timing signoff closure.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Director level

Key Responsibilities

  • •Develop and manage SoC execution schedules, track critical milestones, and communicate status and risks to senior management.
  • •Own optimization of floor-plans, area, and interconnects to meet PPA (Power, Performance, Area) goals during early chip development.
  • •Drive SoC physical design implementation in advanced process nodes and lead a team across physical design, circuit design, DFT, and integration.
  • •Collaborate with global teams across RTL, NPI, packaging, DFT, and architecture to identify improvement opportunities and review design constraints.
  • •Build and oversee automation utilities to optimize chip area, improve quality, and accelerate execution; run design reviews including EMIR analysis and timing signoff closure.

Pay and Benefits

Salary: USD 250,600 - 362,600 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kParental LeaveDisability CoveragePaid HolidaysRsus

Key Requirements

  • •Bachelor’s degree in a technical field (preferably engineering) and 15+ years of experience in the hardware industry with proven management experience leading SoC and Physical Design teams.
  • •Experience leading and managing large ASIC developments in advanced process nodes.
  • •Experience developing Physical Design execution schedules and tracking critical milestones.
  • •Hands-on ASIC design experience from concept through release.
  • •Knowledge of industry-standard PnR and sign-off tools and capabilities.
Experience:15+ yearsHardwareASICSoCSemiconductor
Education:Bachelor's
Skills:LeadershipCross-functional collaborationRisk communicationSelf-motivation
Tech Stack:SoCASICPhysical DesignPnRTiming closureStatic Timing Analysis (STA)EMIR analysisTiming signoffTclPythonRTLNPIPackagingDFTFront-End (FE) flowBack-End (BE) flowPower analysisIntegrity analysisBlock-level synthesisPlace and route

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
Glassdoor
Glassdoor: 4.0
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