Next Gen CPU Power Management RTL Design Engineer

AMD
Santa Clara
Workplace: OnsiteFull timeUSD 145,600 - 249,600 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Debugging","Communication","Teamwork","Cross-functional collaboration"]

Design and develop microarchitecture and RTL for core clocking, reset, and power management IP in next-generation processors. Collaborate with architecture, verification, physical design, and firmware teams to integrate IP using advanced process technologies. Define specs and interfaces, implement Verilog/SystemVerilog optimized for timing/area/power, develop C/C++ firmware for initialization and control, and drive debug across cross-functional teams to ensure functional correctness.

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FursaFursa
AMD
AMD
2 days ago

Next Gen CPU Power Management RTL Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Design and develop microarchitecture and RTL for core clocking, reset, and power management IP in next-generation processors. Collaborate with architecture, verification, physical design, and firmware teams to integrate IP using advanced process technologies. Define specs and interfaces, implement Verilog/SystemVerilog optimized for timing/area/power, develop C/C++ firmware for initialization and control, and drive debug across cross-functional teams to ensure functional correctness.
Location: Santa Clara
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Design and develop microarchitecture for core clocking, reset, and power management IP in next-generation processors.
  • •Collaborate with architecture, design verification, physical design, and firmware teams to integrate IP into the overall processor.
  • •Define specifications and documentation for IP microarchitecture and interfaces.
  • •Implement RTL in Verilog/SystemVerilog optimized for timing, area, power, and performance.
  • •Develop C/C++ firmware for IP initialization, configuration, and control, then support RTL linting/CDC analysis and debug RTL and firmware issues.

Pay and Benefits

Salary: USD 145,600 - 249,600 annually

Key Requirements

  • •MS in EE, ECE, Computer Engineering, or Computer Science, plus 5+ years of experience in RTL design and microarchitecture for processors or complex IP.
  • •Proficiency in Verilog/SystemVerilog for RTL design and verification.
  • •Strong C/C++ development experience, including embedded firmware for power management.
  • •Solid understanding of digital design fundamentals including CDC, multi-voltage, and power-aware design.
  • •Knowledge of low-power methodologies such as clock gating, power gating, and DVFS.
Education:Master's
Skills:DebuggingCommunicationTeamworkCross-functional collaboration
Languages:En-us
Tech Stack:VerilogSystemVerilogCC++RTLCDC

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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