R&D Engineer IC Design 4

Broadcom
United States, Austin
Workplace: OnsiteFull timeUSD 121,900 - 195,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Independent work","Team collaboration","Debugging","Analysis"]

Own front-end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and constraint development. Build and debug designs from systems requirements, performing simulation-based verification plus formal verification and timing analysis after physical implementation. Work with the complete ASIC implementation flow and use tools such as Verilog simulation, PrimeTime, Formality/Conformal, and Spyglass Lint. Collaborate across geographies in a large team.

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FursaFursa
Broadcom
Broadcom
2 months ago

R&D Engineer IC Design 4

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 25 days agoStatus: Live

Job Summary

Own front-end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and constraint development. Build and debug designs from systems requirements, performing simulation-based verification plus formal verification and timing analysis after physical implementation. Work with the complete ASIC implementation flow and use tools such as Verilog simulation, PrimeTime, Formality/Conformal, and Spyglass Lint. Collaborate across geographies in a large team.
Location: United States, Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Perform front-end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and constraint development.
  • •Design logic blocks from systems requirements documents and simulate/debug using Verilog simulation.
  • •Conduct design verification using simulation and formal verification, including analysis of timing from physical implementation.
  • •Use ASIC implementation flow knowledge to support end-to-end integration from RTL synthesis through timing closure.
  • •Collaborate independently and as part of a large, multi-geography team spanning multiple geographies.

Pay and Benefits

Salary: USD 121,900 - 195,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kPaid Leave

Key Requirements

  • •BS/MS in Electrical or Computer Engineering (or equivalent).
  • •Bachelors with 8+ years of related experience, or Masters with 6+ years of related experience.
  • •Experience with complete ASIC or standard product implementation flow from RTL synthesis through timing analysis/closure.
  • •Proficiency with design tools/flows including Verilog simulation and ASIC front-end design and verification.
  • •Working knowledge of TCL/Perl scripting, synthesis (Synopsys Design Compiler or Cadence RTL compiler), and timing/formal verification tools.
Experience:8+ yearsASICSemiconductor
Education:Bachelor's in Electrical or Computer Engineering
Skills:Independent workTeam collaborationDebuggingAnalysis
Tech Stack:VerilogTCLPerlSynopsys Design CompilerCadence RTL compilerPrimeTimeLibertySynopsys FormalityCadence ConformalSpyglass LintDFTScan methodologySVNGitRTL synthesisFormal verificationTiming analysisPower analysisConstraint development

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn