SoC Physical Verification Engineer, HBM

Micron Technology
United States
Workplace: OnsiteFull timeUSD 97,000 - 205,000 annuallyFunction: QA, Test & Release EngineeringEducation: mastersSkills: ["Cross-functional communication","Debugging","Automation mindset","Verification closure ownership"]

Own end-to-end physical verification sign-off for full-chip and hierarchical SoCs in Micron’s Heterogeneous Integration Group, driving DRC/LVS/ERC/PERC, reliability checks, and DFM/antenna compliance. Execute and debug foundry-qualified rule decks, manage waivers, and drive clean closure from RTL-to-GDS flow impacts through tape-out readiness. Automate verification flows with Python/Tcl/Perl, correlate results with post-silicon measurements, and advance AI/ML-based verification and PPA optimization tools.

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FursaFursa
Micron Technology
Micron Technology
4 weeks ago

SoC Physical Verification Engineer, HBM

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Last checked: 17 hours agoStatus: Live

Job Summary

Own end-to-end physical verification sign-off for full-chip and hierarchical SoCs in Micron’s Heterogeneous Integration Group, driving DRC/LVS/ERC/PERC, reliability checks, and DFM/antenna compliance. Execute and debug foundry-qualified rule decks, manage waivers, and drive clean closure from RTL-to-GDS flow impacts through tape-out readiness. Automate verification flows with Python/Tcl/Perl, correlate results with post-silicon measurements, and advance AI/ML-based verification and PPA optimization tools.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: QA, Test & Release Engineering

Key Responsibilities

  • •Lead end-to-end physical verification sign-off for full-chip and hierarchical designs, including DRC, LVS, ERC, PERC, antenna checking, and DFM.
  • •Execute and debug foundry-qualified rule decks, manage waivers, and drive clean closure aligned to advanced-node foundry requirements.
  • •Perform reliability verification across multiple power domains (e.g., ESD, latch-up, electromigration, floating nets, connectivity checks).
  • •Run density, metal fill, and CMP checks for yield-aware manufacturability, including at 3nm and below.
  • •Develop, maintain, and optimize physical verification flows and regression infrastructure, and advance AI/ML-assisted verification and PPA optimization tools.

Pay and Benefits

Salary: USD 97,000 - 205,000 annually
Perks:Health InsuranceDentalVisionPaid LeavePaid HolidaysParental Leave

Key Requirements

  • •Experience with full-chip or block-level physical verification for advanced-node SoCs, memory, or heterogeneous integration designs.
  • •Experience with physical verification methodologies including DRC, LVS, ERC, PERC, DFM, antenna, and reliability sign-off.
  • •Experience using physical verification tools such as Calibre, IC Validator (ICV), Pegasus, or similar, including rule deck development/customization.
  • •Working knowledge of RTL-to-GDS implementation flows, including place-and-route and extraction, and how they impact physical verification outcomes.
  • •Ability to drive verification closure via strong cross-functional communication in a global engineering environment.
Experience:Advanced-node SoCHBMMemoryHeterogeneous integration
Education:Master's
Skills:Cross-functional communicationDebuggingAutomation mindsetVerification closure ownership
Tech Stack:PythonTclPerlCalibreIC Validator (ICV)PegasusEDADRCLVSERCPERCDFMAntenna checkingESDLatch-upElectromigrationRC extractionMachine learningArtificial intelligence

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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