Principal Design Engineer - ( Synthesis/LEC/CLP )

Cadence Design Systems
Bengaluru, Pune
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8-12 yearsEducation: bachelorsSkills: ["Communication","Documentation","Cross-team collaboration","Root-cause resolution","Problem-solving"]

Drive ASIC/SoC design flow excellence across Synthesis, Logical Equivalence Checking (LEC), Conformal Low Power (CLP), and UPF/CPF-based power intent verification. You will improve methodology and best practices, own end-to-end LEC sign-off across multiple blocks (including NEQ/abort debug), and lead physical synthesis closure for complex designs with constraint development and PPA closure. Also manage low-power CLP sign-off and maintain technical documentation and status tracking.

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Cadence Design Systems
Cadence Design Systems
4 days ago

Principal Design Engineer - ( Synthesis/LEC/CLP )

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Last checked: 9 hours agoStatus: Live

Job Summary

Drive ASIC/SoC design flow excellence across Synthesis, Logical Equivalence Checking (LEC), Conformal Low Power (CLP), and UPF/CPF-based power intent verification. You will improve methodology and best practices, own end-to-end LEC sign-off across multiple blocks (including NEQ/abort debug), and lead physical synthesis closure for complex designs with constraint development and PPA closure. Also manage low-power CLP sign-off and maintain technical documentation and status tracking.
Location: Bengaluru, Pune
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Drive methodology improvements and best-practice development across Synthesis, LEC, CLP, and ECO flows.
  • •Own end-to-end LEC sign-off across multiple design blocks, including debug of NEQs and aborts.
  • •Lead physical synthesis closure on complex blocks, including constraint development and PPA closure.
  • •Provide CLP sign-off for low-power intent designs: level shifter, retention, isolation, PSO strategy architecture, and supply set/domain conflict resolution.
  • •Own technical documentation, status tracking, and write-ups across active blocks.

Key Requirements

  • •8–12 years of hands-on ASIC/SoC design experience with strong depth in Synthesis (Genus), LEC (Conformal), and Low Power.
  • •Proven experience across multi-corner, multi-mode sign-off considerations.
  • •Strong scripting ability in TCL, Python, and PERL (etc.).
  • •Deep understanding of ASIC flow interactions: RTL, synthesis, physical design handoff, and DFT.
  • •Excellent written and verbal communication skills for owning technical documentation and cross-team discussions.
Experience:8-12 years
Education:Bachelor's in Electrical/Electronic
Skills:CommunicationDocumentationCross-team collaborationRoot-cause resolutionProblem-solving
Tech Stack:GenusConformalSynthesisLogical Equivalence Checking (LEC)Conformal Low Power (CLP)UPFCPFTCLPythonPERLASIC/SoCRTLPhysical design handoffDFTMulti-cornerMulti-modeNEQsECOPPALevel shifter

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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