Design Verification Engineer

AMD
Santa Clara, Austin
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Communication","Presentation","Collaboration","Mentoring","Knowledge sharing"]

Drive verification for DDR interface server memory products, including DDR5, LPDDR5/LPDDR6, and DFI across DIMMs. Develop and execute verification plans, ensure FW/BIOS/SW alignment with PHY/system behavior, and support RTL-to-system debug in cross-functional collaboration. Build SystemVerilog/UVM-based testbenches, coverage models, VIPs/BFMs, and use assertions, constraints, and formal verification methods to improve validation quality. Mentor and share verification methodology knowledge.

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FursaFursa
AMD
AMD
5 days ago

Design Verification Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live

Job Summary

Drive verification for DDR interface server memory products, including DDR5, LPDDR5/LPDDR6, and DFI across DIMMs. Develop and execute verification plans, ensure FW/BIOS/SW alignment with PHY/system behavior, and support RTL-to-system debug in cross-functional collaboration. Build SystemVerilog/UVM-based testbenches, coverage models, VIPs/BFMs, and use assertions, constraints, and formal verification methods to improve validation quality. Mentor and share verification methodology knowledge.
Location: Santa Clara, Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Drive verification efforts for DDR interfaces across DDR5, LPDDR5/LPDDR6, and DFI in server memory products.
  • •Execute verification plans with a team of verification engineers for DDR5, LPDDR5, and DFI memory systems.
  • •Analyze PHY interaction with the overall system (HW/Silicon, FW, BIOS, SW) to ensure alignment for memory interface features.
  • •Support cross-functional discussions by understanding RTL and micro-architecture for planning and debug.
  • •Support Post-Si issue debug/resolution for product performance, power, and functional issues and contribute to verification methodology knowledge sharing.

Key Requirements

  • •Develop and implement SystemVerilog and UVM-based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems.
  • •Work with hardware, firmware, and software teams to align on system-level memory architecture, identify integration issues, and define validation requirements early.
  • •Build VIPs and BFMs for memory interfaces (preferred).
  • •Demonstrate strong proficiency in SystemVerilog assertions, constraints, and coverage.
  • •Have proven experience with formal verification methods and tool usage beyond standard applications.
Experience:8+ years
Education:Bachelor's
Skills:CommunicationPresentationCollaborationMentoringKnowledge sharing
Tech Stack:SystemVerilogUVMCC++PythonPerlDDRDDR5LPDDR5LPDDR6DFIRTLSimulationFunctional coverageSystemVerilog assertionsConstraintsFormal verificationVIPBFMGLS

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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