Sr. ASIC Design Verification Engineer (Silicon Engineering)

Develop and lead digital ASIC verification for next-generation chips used in Starlink’s space and ground infrastructure. Own block- and system-level verification, writing and reviewing test plans, building test harnesses and sequences, and driving regression runs to close coverage. Collaborate with cross-disciplinary teams on pre-silicon verification, chip bring-up, and post-silicon validation to expand Starlink network performance and capabilities.