Design Verification Engineer

OpenAI
San Francisco
Workplace: OnsiteFull timeUSD 266,000 - 380,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["SystemVerilog","UVM","VCS","Questa","Verdi"]

Design Verification Engineer responsible for verifying IP blocks, subsystems, or full SoC for OpenAI's ML accelerators. Create verification plans from architecture specs, develop SystemVerilog/UVM testbenches, build stimulus generators and scoreboards, drive bug triage, and contribute to regression infrastructure, collaborating with architecture, RTL, software, and systems teams to ensure reliable silicon at scale.

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FursaFursa
OpenAI
OpenAI
9 months ago

Design Verification Engineer

āœ“ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live

Job Summary

Design Verification Engineer responsible for verifying IP blocks, subsystems, or full SoC for OpenAI's ML accelerators. Create verification plans from architecture specs, develop SystemVerilog/UVM testbenches, build stimulus generators and scoreboards, drive bug triage, and contribute to regression infrastructure, collaborating with architecture, RTL, software, and systems teams to ensure reliable silicon at scale.
Location: San Francisco
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • ā€¢Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.
  • ā€¢Define verification plans based on architecture and microarchitecture specs.
  • ā€¢Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.
  • ā€¢Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.
  • ā€¢Drive bug triage, root cause analysis, and work closely with design teams on resolution.

Pay and Benefits

Salary: USD 266,000 - 380,000 annually
Equity and Bonus:Equity

Key Requirements

  • ā€¢BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.
  • ā€¢Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).
  • ā€¢Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.
  • ā€¢Familiarity with performance modeling, formal verification, or emulation is a plus.
  • ā€¢Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.
Experience:3+ yearsHardware verificationAI hardwareML accelerators
Education:Bachelor's
Skills:SystemVerilogUVMVCSQuestaVerdi
Languages:English
Tech Stack:SystemVerilogUVMVCSQuestaVerdi

Company Brief

OpenAI
Develops and deploys advanced generative AI models (including ChatGPT and DALLĀ·E) and AI infrastructure, providing APIs and consumer products to accelerate safe AGI for broad benefit.
Industry: AI & Machine Learning
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Scaleup
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: San Francisco, United States
Founded: 2015
Glassdoor
Glassdoor: 4.4
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