Sr Principal Design Engineer

Cadence Design Systems
Bengaluru, Pune, Noida, Ahmedabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Problem-solving","Collaboration","Communication"]

Lead the RTL design and verification of a DDR Memory Controller IP, collaborating with IP teams to add features, verify across DDR4/LPDDR4, and ensure lint and CDC guideline compliance. Experience with Verilog, SystemVerilog, and UVM is required; AXI3/4 knowledge and prior IP development experience are a plus.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
7 months ago

Sr Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 12 hours agoStatus: Live

Job Summary

Lead the RTL design and verification of a DDR Memory Controller IP, collaborating with IP teams to add features, verify across DDR4/LPDDR4, and ensure lint and CDC guideline compliance. Experience with Verilog, SystemVerilog, and UVM is required; AXI3/4 knowledge and prior IP development experience are a plus.
Location: Bengaluru, Pune, Noida, Ahmedabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Design, implement, and support the RTL for the DDR Memory Controller IP across DDR4/LPDDR4 protocols.
  • •Collaborate with RTL engineers to add features, ensure customer configurations pass verification regressions, and provide customer support.
  • •Ensure RTL design adheres to LINT and CDC design guidelines.
  • •Engage in verification activities, using SystemVerilog and UVM for debugging and validation.
  • •Contribute to IP development processes and work with IP development teams.

Key Requirements

  • •BE/B.Tech/ME/M.Tech in Electrical/Electronics/VLSI with design and verification experience, with a focus on RTL design and development.
  • •RTL Design using Verilog is a must.
  • •SystemVerilog experience and experience with UVM based environment usage/debugging is required.
  • •AXI3/4 experience is desired.
  • •DDR Memory controller and protocol experience is highly desirable; prior experience in RTL design and implementation of complex protocols is a must.
Experience:SemiconductorHardware designEDA
Education:Bachelor's
Skills:Problem-solvingCollaborationCommunication
Tech Stack:VerilogSystemVerilogUVMAXI3AXI4DDR4LPDDR4

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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