SpaceX

3 months ago

Principal ASIC Design Engineer (Starshield)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 11 hours agoStatus: Live

Job Summary

Lead the design of digital ASICs/FPGA blocks for Starshield programs, shaping micro-architecture, RTL in Verilog/SystemVerilog, and coordinating with DSP/RFIC teams to split hardware/software functions. Drive timing, verification, and silicon bring-up in a fast-paced, collaborative environment, with ongoing focus on performance, power, and reliability for space-ground infrastructure.

Location: United States

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Design digital ASICs and/or FPGAs for Starshield projects.
•Define micro-architecture, implement the RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
•Derive specifications for subsystems and circuits and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
•Provide timing constraints for IPs and support the physical implementation team (synthesis, timing closure, formality check).
•Participate in silicon bring-up and validation; assist in the development of automated test lab equipment for lab measurements.

Pay and Benefits

Salary: USD 200,000 - 285,000 annually

Perks:Health InsuranceVisionDental401kPaid LeaveLife InsuranceDisability

Key Requirements

•Bachelor’s degree in electrical engineering, computer engineering, or computer science.
•8+ years of experience in RTL implementation and/or FPGA/ASIC development.
•Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
•Scripting skills (Python, TCL etc.).
•Experience with standard bus protocols (e.g. AXI, AHB, etc.).

Experience:8+ yearsSpaceDefenseSatelliteGovernment

Education:Bachelor's

Skills:Problem-solvingTeam-playerLearning agilityCommunicationAdaptability

Languages:English

Tech Stack:VerilogSystemVerilogPythonTCLVCSQuestaIESSpyglassXilinx VivadoAltera Quartus II

Eligibility

Security Clearance:TS-SCI

Company Brief

SpaceX

Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn

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SpaceX

3 months ago

Principal ASIC Design Engineer (Starshield)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 11 hours agoStatus: Live

Job Summary

Location: United States

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Design digital ASICs and/or FPGAs for Starshield projects.
•Define micro-architecture, implement the RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
•Derive specifications for subsystems and circuits and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
•Provide timing constraints for IPs and support the physical implementation team (synthesis, timing closure, formality check).
•Participate in silicon bring-up and validation; assist in the development of automated test lab equipment for lab measurements.

Pay and Benefits

Salary: USD 200,000 - 285,000 annually

Perks:Health InsuranceVisionDental401kPaid LeaveLife InsuranceDisability

Key Requirements

•Bachelor’s degree in electrical engineering, computer engineering, or computer science.
•8+ years of experience in RTL implementation and/or FPGA/ASIC development.
•Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
•Scripting skills (Python, TCL etc.).
•Experience with standard bus protocols (e.g. AXI, AHB, etc.).

Experience:8+ yearsSpaceDefenseSatelliteGovernment

Education:Bachelor's

Skills:Problem-solvingTeam-playerLearning agilityCommunicationAdaptability

Languages:English

Tech Stack:VerilogSystemVerilogPythonTCLVCSQuestaIESSpyglassXilinx VivadoAltera Quartus II

Eligibility

Security Clearance:TS-SCI

Company Brief

SpaceX

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn