ASIC Design Verification Engineer

AMD
United States
Workplace: OnsiteFull timeUSD 126,700 - 217,200 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Analytical","Problem-solving","Persistence","Teamwork","Mentoring","Verification methodology"]

Own mixed-signal power management verification strategy and drive coverage closure for a full SOC. Develop system- and block-level verification that includes power state transitions, fault/protection scenarios, and boot/reset sequencing, using SystemVerilog/UVM testbench components, sequences, checkers, and assertions. Correlate real-number models of analog blocks, partner across Analog/RTL/Firmware/System teams, support bring-up, and contribute RTL design work as needed.

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FursaFursa
AMD
AMD
1 day ago

ASIC Design Verification Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Own mixed-signal power management verification strategy and drive coverage closure for a full SOC. Develop system- and block-level verification that includes power state transitions, fault/protection scenarios, and boot/reset sequencing, using SystemVerilog/UVM testbench components, sequences, checkers, and assertions. Correlate real-number models of analog blocks, partner across Analog/RTL/Firmware/System teams, support bring-up, and contribute RTL design work as needed.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Own verification strategy, test plan, coverage goals, and verification readiness/signoff for a mixed-signal power management IC.
  • •Develop and execute system-level verification for the full SOC, including boot/reset sequencing, power state transitions, and fault/protection scenarios.
  • •Build and maintain SystemVerilog/UVM system-level testbench components, sequences, checkers, and assertions; ensure firmware behavior via co-simulation.
  • •Create and extend block-level verification and coverage for digital blocks; verify digital/analog interfaces using real-number models (RNM) and correlate to analog behavior.
  • •Partner with RTL/analog/firmware/systems teams on design reviews, failure debug, and post-silicon correlation; contribute RTL design and mentor junior engineers.

Pay and Benefits

Salary: USD 126,700 - 217,200 annually

Key Requirements

  • •Own verification strategy, test plan, and coverage closure for mixed-signal power management ICs through tape-out.
  • •Experience with system-level/SOC-level verification, including boot/reset sequencing, power state transitions, and fault/protection scenarios.
  • •Strong SystemVerilog and UVM skills to build testbench components, sequences, checkers, and assertions.
  • •Ability to read RTL and develop block-level testbenches and coverage, including digital/analog interfaces using real-number models (RNM) such as wreal/nettype real or Verilog-AMS.
  • •Experience with co-simulation/verification (e.g., firmware/RTL co-simulation, post-silicon bring-up/debug, and/or formal verification/SVA or emulation/FPGA prototyping).
Education:Bachelor's in electrical/computer engineering
Skills:CommunicationAnalyticalProblem-solvingPersistenceTeamworkMentoringVerification methodology
Languages:English
Tech Stack:SystemVerilogUVMRTLSystemVerilog RTL designReal-number modeling (RNM)WrealNettype realVerilog-AMSSVAAssertionsCo-simulationFirmware/RTL co-simulationEmulationFPGARegression automation

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn