SR ENGINEER, DDEG Design Methodology
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4-8 yearsEducation: bachelorsSkills: ["Communication","Debugging","Teamwork","Analytical thinking","Judgment"]Own end-to-end verification and analysis of sophisticated full-chip, gate-level custom DRAM designs using advanced low-power and power-management methods across DDR4/LPDDR4/DDR5/LPDDR5. Leverage AI-based tools and automation to speed verification cycles, improve debug efficiency, and validate AI outputs against specs via simulations, waveforms, assertions, and coverage. Build test benches/vectors, develop SV/UVM verification, and collaborate globally using tools like Xcellium, Virtuoso, and SPICE/Verilog-based flows.
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