PD Architect

AMD
Bengaluru
Workplace: OnsiteFull timeINR 7,000,630 - 10,000,900 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 15+ yearsEducation: mastersSkills: ["Leadership","Communication","Project management","Cross-functional collaboration","Detail-oriented"]

Lead the Physical Design (RTL to GDS) implementation and convergence for complex ASICS and APU/dGPU designs within AMD’s S3 India physical design team. Drive PnR, timing, physical verification, and signoff—including IP integration and full-chip flow execution—while guiding a team of silicon design engineers to successful tape-outs. Collaborate cross-functionally and with CAD/EDA vendors to improve PPA and PD closure methodology, ensuring first-pass silicon success in advanced nodes.

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FursaFursa
AMD
AMD
2 days ago

PD Architect

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Job Summary

Lead the Physical Design (RTL to GDS) implementation and convergence for complex ASICS and APU/dGPU designs within AMD’s S3 India physical design team. Drive PnR, timing, physical verification, and signoff—including IP integration and full-chip flow execution—while guiding a team of silicon design engineers to successful tape-outs. Collaborate cross-functionally and with CAD/EDA vendors to improve PPA and PD closure methodology, ensuring first-pass silicon success in advanced nodes.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Manager level

Key Responsibilities

  • •Lead the physical design team for implementation and convergence of highly complex tiles, coordinating PnR and backend convergence activities.
  • •Drive end-to-end delivery of GDS starting from RTL, including signoff and physical verification.
  • •Collaborate with cross-functional teams to improve PPA through continuous PD methodology improvements.
  • •Own timing closure and full-chip integration flows, including both tile-level and FCT timing convergence.
  • •Provide technical direction and guidance/support to the engineering team and collaborate with CAD/EDA vendors to strengthen PD closure methodology.

Pay and Benefits

Salary: INR 7,000,630 - 10,000,900 annually

Key Requirements

  • •15+ years of physical design experience covering RTL to GDS, STA, physical verification, timing signoff, and tapeout delivery.
  • •Ability to drive/manage projects from RTL to GDS, including managing more than 3 tape-outs.
  • •Experience with block-level implementation including floorplanning, timing closure, and physical verification.
  • •Proficiency in physical design verification and signoff techniques such as Formal Equivalence (LEC/FE), VCLP, low power checks, IR&EM, VSI, and timing convergence.
  • •Strong scripting and RTL skills using Perl/TCL/Shell/Python, and Verilog/VHDL, plus experience with industry-standard EDA tools.
Experience:15+ yearsASICsAPU/dGPURTL-to-GDSPhysical designHigh-performance computingSupercomputingAdvanced process nodes
Education:Master's in Computer/Electronics/Electrical Engineering
Skills:LeadershipCommunicationProject managementCross-functional collaborationDetail-oriented
Tech Stack:PnRVCLPFormal EquivalenceLECIR&EMLow Power ChecksSTAVSIFusion CompilerICC2PrimeTimeRedhawkPTPXPerlTCLShellPythonVerilogVHDLGDS

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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