IC Design Engineer

Lead Broadcom’s physical design methodology to achieve right-first-time silicon. Own block/level layout activities including floorplanning, partitioning, placement, clock tree synthesis, routing, and physical verification, working through P&R, extraction, and STA closure. Implement timing and functional ECOs, and build or adapt automation flows to improve quality and turnaround time. Proficient with P&R/PV/STA/ECO using Cadence, Synopsys, or Mentor EDA tools and scripting in Tcl/Perl.