IC Design Engineer

Broadcom
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Analytical skills","Collaboration","Lead by example"]

Lead Broadcom’s physical design methodology to achieve right-first-time silicon. Own block/level layout activities including floorplanning, partitioning, placement, clock tree synthesis, routing, and physical verification, working through P&R, extraction, and STA closure. Implement timing and functional ECOs, and build or adapt automation flows to improve quality and turnaround time. Proficient with P&R/PV/STA/ECO using Cadence, Synopsys, or Mentor EDA tools and scripting in Tcl/Perl.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Broadcom
Broadcom
1 month ago

IC Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 10 days agoStatus: Live

Job Summary

Lead Broadcom’s physical design methodology to achieve right-first-time silicon. Own block/level layout activities including floorplanning, partitioning, placement, clock tree synthesis, routing, and physical verification, working through P&R, extraction, and STA closure. Implement timing and functional ECOs, and build or adapt automation flows to improve quality and turnaround time. Proficient with P&R/PV/STA/ECO using Cadence, Synopsys, or Mentor EDA tools and scripting in Tcl/Perl.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Apply and lead physical design methodology and milestone flow to achieve right-first-time silicon.
  • •Perform block and level layout activities including floorplanning, partitioning, placement, CTS, routing, and physical verification.
  • •Implement timing and functional ECOs and work toward STA closure across P&R, extraction, and physical verification.
  • •Understand SoC top-down and bottom-up physical design integration in 5nm and lower technologies.
  • •Build automation flows or adapt existing ones for reuse to improve TAT with better quality.

Key Requirements

  • •3+ years MSEE/MSCS (or 5+ years BSEE/BSCS) with a deep understanding of backend digital design flow.
  • •Proficiency in timing and physical constraints, including working across floorplan/partition/placement/CTS/route stages for SoC top-level.
  • •Experience with P&R flows and ability to quickly catch up on internal flows and adapt.
  • •Proficient with backend EDA tools such as Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, and Redhawk.
  • •Proficiency in Tcl and Perl, with excellent analytical skills and ability to collaborate cross-site/cross-time zone.
Experience:SoCBackend digital design
Education:Master's
Skills:Analytical skillsCollaborationLead by example
Tech Stack:CadenceSynopsysMentorSoCFloor-planningPartitioningPlacementClock tree synthesisRoutePhysical verificationP&RExtractionSTAECOGenusInnovusQuantusTempusDCStar-RCXT

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn