SOC Physical Design and STA Methodology Engineer

The role focuses on SoC physical design flow and methodology development at SSIR in Bangalore, driving PnR/STA flows, ECO implementation, and automation. You will script EDA tools, optimize timing and power, work with multi-node designs, and collaborate with partition and full-chip teams to push PPA and reliability across advanced process nodes. A strong background in PnR, STA, and EDA tools is essential.