Lead Design Verification Engineer

AMD
Hyderabad
Workplace: OnsiteFull timeINR 2,186,520 - 3,123,600 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: mastersSkills: ["Teamwork","Communication","Analytical thinking","Problem-solving","Collaboration"]

Drive design verification for Network-on-Chip (NoC) IPs, subsystems, and SoC designs by architecting and building simulation and/or formal verification environments. Collaborate with architects and design engineers to plan test strategies, develop SystemVerilog/UVM testbenches, and create constrained-random and assertion-based verification. Debug failures, write and analyze coverage to achieve closure, and support automation and regressions for complex ASIC/FPGA and VLSI development.

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FursaFursa
AMD
AMD
2 days ago

Lead Design Verification Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live

Job Summary

Drive design verification for Network-on-Chip (NoC) IPs, subsystems, and SoC designs by architecting and building simulation and/or formal verification environments. Collaborate with architects and design engineers to plan test strategies, develop SystemVerilog/UVM testbenches, and create constrained-random and assertion-based verification. Debug failures, write and analyze coverage to achieve closure, and support automation and regressions for complex ASIC/FPGA and VLSI development.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Plan verification of complex digital design blocks by understanding architecture and design specifications.
  • •Create comprehensive verification testplans by partnering with architects and design engineers.
  • •Design and architect SystemVerilog/UVM testbenches and constrained-random/direct verification environments.
  • •Formally verify designs using SystemVerilog assertions and industry formal tools, then debug failures with design engineers.
  • •Define coverage measures, run coverage analysis, and close coverage metrics; support regressions and automation using scripting.

Pay and Benefits

Salary: INR 2,186,520 - 3,123,600 annually

Key Requirements

  • •5+ years of verification experience in ASIC and/or full custom chip development phases.
  • •Proficiency developing UVM/OVM/VMM and SystemVerilog/Verilog testbenches using simulation and debug tools such as Synopsys VCS and Cadence IES.
  • •Strong knowledge of assertion and coverage-driven verification techniques.
  • •Experience designing verification environments and test plans, including functional coverage measures and achieving coverage closure.
  • •Knowledge of protocols such as AXI3/4, DDR4/5, HBM, or PCIe is a plus; NOC verification experience is a plus.
Experience:5+ yearsASICFPGASoCVLSINetwork on ChipFormal verification
Education:Master's
Skills:TeamworkCommunicationAnalytical thinkingProblem-solvingCollaboration
Languages:En-us
Tech Stack:System VerilogUVMOVMVMMVerilogSystem Verilog Assertions (SVA)Synopsys VCSCadence IESSynopsys VC-FormalCadence IEVJasperMagellanPerlAXI3AXI4DDR4DDR5HBMPCIeSystem-on-Chip

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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