Lead IP/SoC level design verification

AMD
Hyderabad
Workplace: OnsiteFull timeINR 4,860,800 - 6,944,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: bachelorsSkills: ["Communication","Teamwork","Analytical thinking","Problem-solving","Mentorship"]

Plan, build, and execute verification for AMD Soft IP cores, ensuring silicon-proven quality across supported platforms with zero escapes to production. Partner with IP designers and architects to define verification strategies (test plans, coverage models), develop assertion-based and constrained-random tests, and apply formal verification where applicable. Drive verification closure through coverage metrics and quality sign-off, improve UVM/SystemVerilog practices, and maintain regression + CI/CD verification infrastructure.

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FursaFursa
AMD
AMD
1 day ago

Lead IP/SoC level design verification

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 8 hours agoStatus: Live

Job Summary

Plan, build, and execute verification for AMD Soft IP cores, ensuring silicon-proven quality across supported platforms with zero escapes to production. Partner with IP designers and architects to define verification strategies (test plans, coverage models), develop assertion-based and constrained-random tests, and apply formal verification where applicable. Drive verification closure through coverage metrics and quality sign-off, improve UVM/SystemVerilog practices, and maintain regression + CI/CD verification infrastructure.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Collaborate with IP designers, architects, and application engineers to understand features and parameterization requirements.
  • •Develop verification strategies (test plans and functional coverage models) using ABV and constrained-random verification, including formal verification where applicable.
  • •Build and document test plans covering functional coverage, parameter space, platform interactions, and end-user use cases; estimate effort for test development and verification environment updates.
  • •Develop directed and constrained-random verification tests with parameter configuration and coverage-closure strategies; drive verification closure using metrics, bug convergence, and quality sign-off criteria.
  • •Review verification architecture, testbench design, and coding standards; promote UVM/SystemVerilog best practices and improve regression + CI/CD verification infrastructure.

Pay and Benefits

Salary: INR 4,860,800 - 6,944,000 annually

Key Requirements

  • •10+ years of industry experience in IP/SoC level design verification.
  • •Proficient in IP-level ASIC or FPGA functional verification.
  • •Hands-on debugging of RTL using industry-standard simulation tools (Questa, Xcelium, VCS, Vivado Simulator).
  • •Proficient in UVM-based testbench development with constrained-random verification and functional/code coverage closure.
  • •Strong experience with SystemVerilog/UVM, assertion-based verification (SVA/PSL), and formal verification tools/methodologies.
Experience:10+ yearsSemiconductorsSoCIP verificationASICFPGARTL verificationFormal verificationUVMConstrained-random verification
Education:Bachelor's in computer engineering/Electrical Engineering
Skills:CommunicationTeamworkAnalytical thinkingProblem-solvingMentorship
Languages:English
Tech Stack:SystemVerilogUVMAssertion-based verificationABVConstrained-random verificationSVAPSLQuestaXceliumVCSVivado SimulatorUVM methodologyAI-assisted verification toolsVerification automation frameworksUVM-based testbenchRegression infrastructureCI/CDPythonPerlShell

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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