Sr. Silicon Design Engineer
AMD
San Jose
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Teamwork","Analytical skills","Problem-solving","Innovative mindset"]Design and verify RTL for high-performance, multi-protocol wireline SerDes PHY components in advanced CMOS processes. You’ll collaborate with system link architects to micro-architect SerDes PHY designs, develop RTL for calibration/adaptation and clock-data-recovery blocks, apply low-power techniques with PPA analysis, and run verification plus design-rule checks (LINT/CDC/RDC). You’ll also support debug, static timing closure, and silicon bring-up/sign-off with physical design and validation teams.

