Physical Design Engineer

Etched
Austin
Workplace: OnsiteFull timeUSD 150,000 - 275,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5-10 yearsSkills: ["Collaboration","Problem-solving","Teamwork","Communication"]

Physical Design Engineer at Etched responsible for block-level implementation and verification, driving timing closure and PPA optimization, and supervising 3rd party design work. Collaborates with RTL designers to improve PPA, builds dashboards for PD project convergence, and optimizes CAD/EDA tool flows. Requires 5-10+ years in PD, with back-end design, timing closure, and scripting skills; role based in Austin with periodic collaboration in San Jose.

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Etched
Etched
5 months ago

Physical Design Engineer

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Last checked: 6 hours agoStatus: Live

Job Summary

Physical Design Engineer at Etched responsible for block-level implementation and verification, driving timing closure and PPA optimization, and supervising 3rd party design work. Collaborates with RTL designers to improve PPA, builds dashboards for PD project convergence, and optimizes CAD/EDA tool flows. Requires 5-10+ years in PD, with back-end design, timing closure, and scripting skills; role based in Austin with periodic collaboration in San Jose.
Location: Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Deeply understand what is involved in physical design and apply it to block-level implementation and verification.
  • •Run PD flows to close blocks, support ASIC infrastructure, automate PD flows, and improve CAD infrastructure.
  • •Collaborate with RTL designers and provide Physical Design feedback to improve PPA.
  • •Drive dashboards that show the convergence of projects related to PD.
  • •Optimize tool flows, working with EDA vendors to incorporate the latest features.

Pay and Benefits

Salary: USD 150,000 - 275,000 annually
Equity and Bonus:Equity
Perks:MedicalDentalVisionHousing SubsidyRelocationMeal AllowanceEquity

Key Requirements

  • •5-10+ years of previous experience with PD
  • •Experience with back-end design and timing closure on advanced process nodes (5nm and below)
  • •Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows
  • •Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
  • •Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
Experience:5-10 yearsSemiconductorHardwareIC design
Skills:CollaborationProblem-solvingTeamworkCommunication
Tech Stack:CadenceInnovusGenusICC2Fusion CompilerPrimeTimeTempusVoltusGDSIIUPFRTLPythonEDAScripting

Company Brief

Etched
Designs transformer‑specialized AI inference ASICs (product: Sohu) to accelerate large‑language‑model workloads, working with TSMC for fabrication and targeting energy‑efficient inference performance.
Industry: Hardware Devices
Company Size: Medium (51 to 250 employees)
Growth: Early Stage Startup
Valuation: Unicorn (USD 1B+)
Funding: Series A
Headquarters: San Jose, United States
Founded: 2022
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