Senior Mask Layout Design Engineer

NVIDIA
Taipei
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Teamwork","Interpersonal skills","Debugging","Attention to detail","Passion"]

Perform physical mask/layout for high-speed mixed-signal blocks such as PLLs, SerDes, ADCs, and ESD structures in sub-micron CMOS using Cadence tools. Partner with ASIC and mixed-signal engineers to tailor VLSI designs, contribute to floorplanning, custom layout, and rule/schematic verification, and run/debug verification flows (DRC/LVS) including deck customization. Leverage Cadence Virtuoso and scripting (Perl/Python/SKILL).

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FursaFursa
NVIDIA
NVIDIA
2 weeks ago

Senior Mask Layout Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 21 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Perform physical mask/layout for high-speed mixed-signal blocks such as PLLs, SerDes, ADCs, and ESD structures in sub-micron CMOS using Cadence tools. Partner with ASIC and mixed-signal engineers to tailor VLSI designs, contribute to floorplanning, custom layout, and rule/schematic verification, and run/debug verification flows (DRC/LVS) including deck customization. Leverage Cadence Virtuoso and scripting (Perl/Python/SKILL).
Location: Taipei
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Perform physical mask layout for high-speed mixed-signal functions (PLL, SerDes, ADCs, ESD structures) in sub-micron CMOS using Cadence tools.
  • •Collaborate cross-functionally with ASIC and mixed-signal engineers to customize designs for VLSI product integration.
  • •Handle floorplanning and custom layout activities for selected blocks.
  • •Verify layout against design rules and schematics.
  • •Run and debug verification flows and customize decks for DRC/LVS checking.

Key Requirements

  • •BSEE or equivalent experience.
  • •5+ years of proven experience in mask and layout design.
  • •Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
  • •Expertise with Cadence custom circuit design tools, particularly Virtuoso.
  • •Experience running/debugging verification tools including Dracula, Hercules, Calibre, and Primeyield.
Experience:5+ yearsSemiconductorASICVLSIMixed-signalCMOS
Education:Bachelor's
Skills:TeamworkInterpersonal skillsDebuggingAttention to detailPassion
Tech Stack:CadenceVirtuosoDraculaHerculesCalibrePrimeyieldPerlPythonSKILLDRCLVSASICVLSICMOSPLLSerDesAnalog to Digital convertersESDSub-micron CMOS

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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