Lead Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["RTL","SerDes","USB","PCIe","MIPI","HDMI","LINT","SDC","CDC","DFT","Synth","PnR","PLL"]

Lead Design Engineer responsible for RTL coding and datapath design for high-speed SerDes IPs, ensuring complete design flows with rigorous checks (LINT, SDC, CDC, DFT, CLP, Synth, PnR). Collaborates with analog and digital teams, working on microarchitecture, IP calibration, and high-speed digital circuits across multiple technology nodes.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
4 months ago

Lead Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live
Reposted: similar role first listed 1 year ago

Job Summary

Lead Design Engineer responsible for RTL coding and datapath design for high-speed SerDes IPs, ensuring complete design flows with rigorous checks (LINT, SDC, CDC, DFT, CLP, Synth, PnR). Collaborates with analog and digital teams, working on microarchitecture, IP calibration, and high-speed digital circuits across multiple technology nodes.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Lead the design and verification of RTL and datapath components for SerDes IPs with a focus on performance and reliability.
  • •Collaborate with analog/design teams to develop algorithms and high-speed digital circuits, ensuring seamless integration across mixed-signal environments.
  • •Ensure adherence to design flows and rigorous checks (LINT, SDC, CDC, DFT, CLP, Synth, PnR) prior to handoff to other teams or customers.
  • •Contribute to micro-architectural decisions and synthesis strategies to optimize IP performance across technology nodes.
  • •Mentor and guide junior engineers in implementing PLLs, dividers, and calibration techniques for signal processing IPs.

Key Requirements

  • •Proficient in RTL coding and datapath designs; experience with complex FIFO design.
  • •Strong knowledge of complete design flows and rigorous checks before delivery to other teams or customers (LINT, SDC, CDC, DFT, CLP, Synth and trial PnR).
  • •Good experience of microarchitecture, design, and synthesis for a complex SerDes IP across technology nodes.
  • •Knowledge of high-speed protocols (USB, PCIe, MIPI (DPHY), HDMI/Display).
  • •Collaborates with Analog design teams to co-develop algorithms and feedback design loops; understanding signal processing IPs, calibrations, PLLs, and dividers.
Experience:SemiconductorsIP designSerDes
Skills:RTLSerDesUSBPCIeMIPIHDMILINTSDCCDCDFTSynthPnRPLL
Languages:English
Tech Stack:RTLSerDesUSBPCIeMIPIHDMILINTSDCCDCDFTSynthPnRPLL

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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