Samsung

4 months ago

SOC RTL Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Seeking a hands-on RTL Design Engineer to join the System Architecture and Design team in SSIR, Bangalore. You will integrate and design IP/BLK RTL at IP level, work on high-speed serdes domains (USB/UFS, PCIe, Ethernet, CSI/DSI/eDP), and collaborate with DV/DFT/PD to ensure RTL quality and constraints are met, including SDC, DFT strategies, and scripting tasks.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Part of System Architecture and Design team; responsible for IP/BLK level RTL integration and design of IP/glues/wrappers with complex high-speed protocol integration; collaborate with DV, DFT, PD cross-functional teams.
•Handle collaterals/reviews for cross-functional teams (test plan/coverage reviews, synthesis/constraints QC, DFT insertion, HIP, SCAN strategies and QC at RTL level).
•Ensure RTL design adheres to design constraints (SDC) at IP/BLK or flat level and manage QC flows; assist with AFL/XPROP/DFT as needed.
•Support scripting tasks using Perl/Python/TCL to automate flows and checks.
•Maintain awareness of domains such as Storage USB/UFS, High-Speed PCIe, Ethernet, CSI/DSI/eDP, Memory LPDDR, HBM and standards like MIPI, DFI, and AMBA.

Key Requirements

•Hands on experience in Front end RTL design, Integration, architecture, coding at IP Level.
•Domain Experience in High Speed Serdes design is preferred (Storage USB/UFS, High-Speed PCIe, Ethernet, Display/Multi-media CSI/DSI/eDP, Memory LPDDR, HBM).
•Good protocol understanding on standard interfaces such as MIPI (CD, M-PHY), DFI Protocols and AMBA.
•Hands-on experience on tools - LINT, VCLP, CDC, RDC, SYNTHESIS, Megagal/ Megagal an are must have skills.
•Design Constraints (SDC) handling at IP/BLK or flat level and respective QC flows; AFL/XPROP/DFT knowledge a plus; scripting in Perl/Python/TCL.

Experience:4-7 yearsSemiconductorHardwareRTL designHigh-speed serdes

Education:Bachelor's

Skills:RTL designVerilogSystemVerilogSynthesisDFTLINTVCLPCDCRDCSYNTHESISMegagalanAFLXPROPPythonPerlTCLAMBAMIPIPCIeUSB

Tech Stack:VerilogSystemVerilogSynthesisLINTVCLPCDCRDCMegagalanAFLXPROPPerlPythonTCLAMBAMIPIPCIeUSBUFSCSIDSI

Company Brief

Samsung

Global conglomerate known for consumer electronics, home appliances, semiconductors, displays, and mobile devices. Designs and manufactures a wide range of products and solutions for consumers, enterprises, and industrial customers worldwide.

Industry: Conglomerates & Holding Companies

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Seoul, South Korea

Founded: 1938

Glassdoor: 3.7

Website LinkedIn

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Samsung

4 months ago

SOC RTL Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Part of System Architecture and Design team; responsible for IP/BLK level RTL integration and design of IP/glues/wrappers with complex high-speed protocol integration; collaborate with DV, DFT, PD cross-functional teams.
•Handle collaterals/reviews for cross-functional teams (test plan/coverage reviews, synthesis/constraints QC, DFT insertion, HIP, SCAN strategies and QC at RTL level).
•Ensure RTL design adheres to design constraints (SDC) at IP/BLK or flat level and manage QC flows; assist with AFL/XPROP/DFT as needed.
•Support scripting tasks using Perl/Python/TCL to automate flows and checks.
•Maintain awareness of domains such as Storage USB/UFS, High-Speed PCIe, Ethernet, CSI/DSI/eDP, Memory LPDDR, HBM and standards like MIPI, DFI, and AMBA.

Key Requirements

•Hands on experience in Front end RTL design, Integration, architecture, coding at IP Level.
•Domain Experience in High Speed Serdes design is preferred (Storage USB/UFS, High-Speed PCIe, Ethernet, Display/Multi-media CSI/DSI/eDP, Memory LPDDR, HBM).
•Good protocol understanding on standard interfaces such as MIPI (CD, M-PHY), DFI Protocols and AMBA.
•Hands-on experience on tools - LINT, VCLP, CDC, RDC, SYNTHESIS, Megagal/ Megagal an are must have skills.
•Design Constraints (SDC) handling at IP/BLK or flat level and respective QC flows; AFL/XPROP/DFT knowledge a plus; scripting in Perl/Python/TCL.

Experience:4-7 yearsSemiconductorHardwareRTL designHigh-speed serdes

Education:Bachelor's

Skills:RTL designVerilogSystemVerilogSynthesisDFTLINTVCLPCDCRDCSYNTHESISMegagalanAFLXPROPPythonPerlTCLAMBAMIPIPCIeUSB

Tech Stack:VerilogSystemVerilogSynthesisLINTVCLPCDCRDCMegagalanAFLXPROPPerlPythonTCLAMBAMIPIPCIeUSBUFSCSIDSI

Company Brief

Samsung

Industry: Conglomerates & Holding Companies

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Seoul, South Korea

Founded: 1938

Glassdoor: 3.7

Website LinkedIn