Senior ASIC Physical Design Engineer, Netlisting

NVIDIA
United States
Workplace: HybridFull timeUSD 136,000 - 264,500 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["Debugging","Problem-solving","Workflow improvement","Productivity mindset"]

Drive physical design for high-frequency, low-power CPUs, GPUs, and SoCs across block, cluster, and full-chip levels, with a focus on netlist-related work like equivalence checking, asynchronous checks (including clock-domain-crossing), MTBF analysis, logic synthesis, and netlist quality checks. Lead timing convergence, timing constraints generation and management, and ECO generation/implementation, leveraging industry EDA tools and RTL/logic design expertise.

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FursaFursa
NVIDIA
NVIDIA
1 month ago

Senior ASIC Physical Design Engineer, Netlisting

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live

Job Summary

Drive physical design for high-frequency, low-power CPUs, GPUs, and SoCs across block, cluster, and full-chip levels, with a focus on netlist-related work like equivalence checking, asynchronous checks (including clock-domain-crossing), MTBF analysis, logic synthesis, and netlist quality checks. Lead timing convergence, timing constraints generation and management, and ECO generation/implementation, leveraging industry EDA tools and RTL/logic design expertise.
Location: United States
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Drive physical design for high-frequency, low-power CPUs, GPUs, and SoCs from block/cluster to full-chip, focusing on netlist-related work (equivalence checking, asynchronous checking, CDC checks, MTBF analysis, logic synthesis, netlist quality).
  • •Support physical design efforts including timing convergence, timing constraints generation and management, and ECO generation and implementation.

Pay and Benefits

Salary: USD 136,000 - 264,500 annually
Equity and Bonus:Equity

Key Requirements

  • •BS (or equivalent) in Electrical or Computer Engineering with 5+ years of experience, or MS (or equivalent) with 3+ years of experience.
  • •Expertise in logic equivalence checking/FV from RTL to tapeout, plus hands-on RTL/logic design skills for timing closure.
  • •Experience with clock-domain-crossing checking and MTBF analysis using industry-standard or in-house tools.
  • •Background in logic synthesis at block or full-chip level, including project execution and/or flow development.
  • •Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation/management, and timing convergence.
Experience:3+ years
Education:Bachelor's in Electrical or Computer Engineering
Skills:DebuggingProblem-solvingWorkflow improvementProductivity mindset
Tech Stack:PerlTCLMakePythonStatic Timing Analysis (STA)Equivalence checkingClock-domain-crossing (CDC)MTBF analysisLogic synthesisRTL

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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Glassdoor: 4.3
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