Senior ASIC Physical Design Engineer, Netlisting

Drive physical design for high-frequency, low-power CPUs, GPUs, and SoCs across block, cluster, and full-chip levels, with a focus on netlist-related work like equivalence checking, asynchronous checks (including clock-domain-crossing), MTBF analysis, logic synthesis, and netlist quality checks. Lead timing convergence, timing constraints generation and management, and ECO generation/implementation, leveraging industry EDA tools and RTL/logic design expertise.