IC Layout Engineering Intern m/f/d

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Work with experienced layout engineers and the analog/mixed-signal design team to implement and verify physical IC layouts in BiCMOS technologies. Learn the analog layout implementation flow using Cadence Virtuoso XL, create transistor-level layouts for key analog blocks, perform layout verification (DRC and layout vs. schematic), and support floorplanning, matching requirements, and the full design flow up to mask generation.

Location: Germany

Workplace: Onsite

Employment Type: Internship

Job Function: Healthcare (Clinical, Medical, Wellness)

Seniority: Intern level

Key Responsibilities

•Learn the analog layout implementation flow using Cadence Virtuoso XL.
•Create transistor-level layouts of analog-specific blocks.
•Acquire experience with analog layout matching techniques and define block-level matching requirements with design engineers.
•Support floor planning and align block-level definitions with top-level requirements.
•Perform layout verification using Design Rule Check and Layout vs. Schematic, and understand database structure and revision control up to mask generation.

Key Requirements

•Completed 4 or 5 semesters of Bachelor study in Electrical or Computer Engineering.
•Pursuing an undergraduate or graduate degree in Electrical Engineering or related degree.
•Cumulative 3.0/4.0 GPA or higher.
•Experience with Linux, scripting and programming.
•Knowledge of IC layout tools (Cadence IC Design Suite) is a strong plus.

Experience:SemiconductorsAnalogMixed signal

Education:Bachelor's in Electrical or Computer Engineering

Skills:CommunicationTeamworkProblem-solvingTroubleshootingSelf-motivation

Languages:EnglishGerman

Tech Stack:Cadence Virtuoso XLCadence IC Design SuiteBiCMOSLinux

Company Brief

Texas Instruments

Industry: Electronics Manufacturing

Website

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Texas Instruments

4 weeks ago

IC Layout Engineering Intern m/f/d

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Location: Germany

Workplace: Onsite

Employment Type: Internship

Job Function: Healthcare (Clinical, Medical, Wellness)

Seniority: Intern level

Key Responsibilities

•Learn the analog layout implementation flow using Cadence Virtuoso XL.
•Create transistor-level layouts of analog-specific blocks.
•Acquire experience with analog layout matching techniques and define block-level matching requirements with design engineers.
•Support floor planning and align block-level definitions with top-level requirements.
•Perform layout verification using Design Rule Check and Layout vs. Schematic, and understand database structure and revision control up to mask generation.

Key Requirements

•Completed 4 or 5 semesters of Bachelor study in Electrical or Computer Engineering.
•Pursuing an undergraduate or graduate degree in Electrical Engineering or related degree.
•Cumulative 3.0/4.0 GPA or higher.
•Experience with Linux, scripting and programming.
•Knowledge of IC layout tools (Cadence IC Design Suite) is a strong plus.

Experience:SemiconductorsAnalogMixed signal

Education:Bachelor's in Electrical or Computer Engineering

Skills:CommunicationTeamworkProblem-solvingTroubleshootingSelf-motivation

Languages:EnglishGerman

Tech Stack:Cadence Virtuoso XLCadence IC Design SuiteBiCMOSLinux

Company Brief

Texas Instruments

Industry: Electronics Manufacturing

Website