Mixed Signal Logic Design Engineer
Penang
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["RTL","Verilog","VHDL","Circuit simulation","Analog modeling"]Develops RTL logic design and simulations for mixed signal IPs and subsystems, contributing to architecture decisions and ensuring designs meet power, performance, area, and timing goals for SoC integration in a hybrid work model at an Intel site in Penang.
