Senior Analog Layout Designer

Olix
Austin
Workplace: OnsiteFull timeUSD 292,000 - 292,000 annuallyFunction: Hardware, Embedded & Systems EngineeringSkills: ["Communication"]

Create and support analog layout for OLIX RX/TX lane macros, collaborating on lane-level integration and tape-out verification. You’ll own major FinFET layout macros, perform block/macro floorplanning, routing, clock and power grid implementation, and ensure device matching, symmetry, and noise isolation. The role also includes running and debugging LVS/ERC/DRC/DFM/Density/antenna checks and EM/IR analysis using Cadence Virtuoso and Calibre/Pegasus, with scripting support via SKILL/TCL/Python.

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Olix
Olix
1 day ago

Senior Analog Layout Designer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 8 hours agoStatus: Live

Job Summary

Create and support analog layout for OLIX RX/TX lane macros, collaborating on lane-level integration and tape-out verification. You’ll own major FinFET layout macros, perform block/macro floorplanning, routing, clock and power grid implementation, and ensure device matching, symmetry, and noise isolation. The role also includes running and debugging LVS/ERC/DRC/DFM/Density/antenna checks and EM/IR analysis using Cadence Virtuoso and Calibre/Pegasus, with scripting support via SKILL/TCL/Python.
Location: Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Create layouts for RX/TX lane macros and support lane-level integration
  • •Own major analog layout macros through tape-outs with FinFET processes
  • •Perform block/macro floor-planning, routing, clock distribution, and power grid implementation
  • •Apply layout considerations for device matching, symmetry, parasitic reduction, and noise isolation
  • •Run and debug LVS/ERC/DRC/DFM/Density/DFM/Density/DFM/Antenna checks and conduct EM/IR analysis

Pay and Benefits

Salary: USD 292,000 annually
Equity and Bonus:Equity
Perks:EquityRetirementAnnual Bonus

Key Requirements

  • •7+ years of Analog Layout Design experience
  • •Understanding of semiconductor fabrication processes and device/layout cross-sections
  • •Minimum 3 years with TSMC FinFET processes (2nm, 3nm, 4nm, 5nm)
  • •Several tape-outs owning major layout macros (ADC, DAC, TIA, CDR, PLL, BGB, LDO)
  • •Expert knowledge running and debugging LVS/ERC/DRC/Density/DFM/Antenna verifications and EM/IR analysis
Experience:SemiconductorsASICFinFET
Skills:Communication
Tech Stack:Cadence VirtuosoCalibrePegasusSKILLTCLPythonLVSERCDRCEM/IR

Company Brief

Olix
Olix designs and manufactures optical processors (Optical Tensor Processing Units) for training and running inference on large AI models, aiming to deliver higher performance and lower energy consumption than conventional silicon-based accelerators.
Industry: Deep Tech
Company Size: Medium (51 to 250 employees)
Growth: Early Stage Startup
Headquarters: London, United Kingdom
Founded: 2024
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