NVIDIA

2 months ago

Senior Photonic Layout Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Lead the physical design and verification of cutting-edge photonic integrated circuits. Collaborate with photonics, CMOS, packaging and systems teams to drive Silicon Photonics (SiPh) and SERDES products from proof-of-concept to high-volume manufacturing, owning tape-out, verification, test structures, and AI-assisted design workflows to improve yield and reduce development cycle times.

Location: Santa Clara

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Take ownership of the physical design and verification of photonic integrated circuits, guiding designs from concept to manufacturing readiness.
•Lead layout execution, tape-out ownership including floor planning, waveguide routing and mask data preparation for high-density photonic devices.
•Perform post-layout verification (DRC, LVS, fill, density) across multiple iterations to ensure tape-out readiness and yield.
•Develop complex test structures, active/passive full loops, and DOEs to optimize process windows and validate designs.
•Develop and apply AI-assisted design methods and layout automation scripts to improve productivity and reduce development cycle times.

Pay and Benefits

Salary: USD 132,000 - 235,750 annually

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•BS, MS, or Ph.D. in Electrical Engineering, Physics, or closely related field (or equivalent experience).
•At least 6+ years of hands-on, full-chip layout design experience in semiconductor, analog, or silicon photonics industries.
•Deep understanding of analog circuit layout, Silicon Photonic constraints, and device physics within advanced sub-micron CMOS and SiPh technologies.
•Proven expertise with Cadence Virtuoso (Custom Layout, SDL) and industry-standard verification suites (Calibre, Hercules, ICV, Dracula, or Primeyield).
•Strong proficiency in programming and scripting languages (Python, SKILL, Perl, TCL, or C++) for layout automation, file I/O, data processing, and tape-out flows.

Experience:6+ yearsSilicon photonicsSemiconductorPhotonicElectronics

Education:Bachelor's

Skills:Cadence VirtuosoPythonC++PerlTCLSKILLCalibreDRCLVSICVDraculaPrimeYieldAutomation

Tech Stack:Cadence VirtuosoCalibreHerculesICVDraculaPrimeYieldPythonSKILLPerlTCLC++

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

2 months ago

Senior Photonic Layout Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Location: Santa Clara

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Take ownership of the physical design and verification of photonic integrated circuits, guiding designs from concept to manufacturing readiness.
•Lead layout execution, tape-out ownership including floor planning, waveguide routing and mask data preparation for high-density photonic devices.
•Perform post-layout verification (DRC, LVS, fill, density) across multiple iterations to ensure tape-out readiness and yield.
•Develop complex test structures, active/passive full loops, and DOEs to optimize process windows and validate designs.
•Develop and apply AI-assisted design methods and layout automation scripts to improve productivity and reduce development cycle times.

Pay and Benefits

Salary: USD 132,000 - 235,750 annually

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•BS, MS, or Ph.D. in Electrical Engineering, Physics, or closely related field (or equivalent experience).
•At least 6+ years of hands-on, full-chip layout design experience in semiconductor, analog, or silicon photonics industries.
•Deep understanding of analog circuit layout, Silicon Photonic constraints, and device physics within advanced sub-micron CMOS and SiPh technologies.
•Proven expertise with Cadence Virtuoso (Custom Layout, SDL) and industry-standard verification suites (Calibre, Hercules, ICV, Dracula, or Primeyield).
•Strong proficiency in programming and scripting languages (Python, SKILL, Perl, TCL, or C++) for layout automation, file I/O, data processing, and tape-out flows.

Experience:6+ yearsSilicon photonicsSemiconductorPhotonicElectronics

Education:Bachelor's

Skills:Cadence VirtuosoPythonC++PerlTCLSKILLCalibreDRCLVSICVDraculaPrimeYieldAutomation

Tech Stack:Cadence VirtuosoCalibreHerculesICVDraculaPrimeYieldPythonSKILLPerlTCLC++

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor