Custom HBM Architecture and Design Engineer

Micron Technology
United States
Workplace: OnsiteFull timeUSD 165,000 - 329,000 annuallyFunction: Architecture & Urban PlanningExperience: 10+ yearsSkills: ["Root-cause analysis","Debugging","Cross-functional collaboration","Technical documentation","Design review participation"]

Work on next-generation HBM SoC logic die architecture and RTL design within the Heterogeneous Integration Group. You will architect and implement SoC-level blocks and memory subsystems, integrate internal and third-party IP, and translate specifications into robust RTL. Partner with verification, physical design, firmware, and product teams to complete SoC integration, support pre/post-silicon validation, and perform root-cause analysis while ensuring manufacturable, high-performance designs.

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FursaFursa
Micron Technology
Micron Technology
1 week ago

Custom HBM Architecture and Design Engineer

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Last checked: 58 minutes agoStatus: Live

Job Summary

Work on next-generation HBM SoC logic die architecture and RTL design within the Heterogeneous Integration Group. You will architect and implement SoC-level blocks and memory subsystems, integrate internal and third-party IP, and translate specifications into robust RTL. Partner with verification, physical design, firmware, and product teams to complete SoC integration, support pre/post-silicon validation, and perform root-cause analysis while ensuring manufacturable, high-performance designs.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Architecture & Urban Planning

Key Responsibilities

  • •Architect, design, and implement RTL for SoC-level blocks and subsystems used in an HBM logic die.
  • •Architect and design memory subsystems, including memory IP selection and integration, bus/protocol selection, and power/performance/area optimization.
  • •Integrate internal and third-party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic).
  • •Support SoC-level integration activities (clocking, reset, power intent, and configuration infrastructure) and assist with pre-silicon validation and post-silicon bring-up.
  • •Contribute to design documentation, block specifications, design reviews, and conduct root-cause analysis for silicon issues while collaborating cross-functionally.

Pay and Benefits

Salary: USD 165,000 - 329,000 annually
Perks:Health InsuranceDentalVisionPaid LeavePaid HolidaysIncome Protection

Key Requirements

  • •Bachelor’s or master’s degree in electrical engineering, computer engineering, or related field, with a minimum of 10 years of experience in a related field.
  • •Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
  • •Experience with the RTL-to-GDS flow, including synthesis and static timing analysis, and sign-off considerations.
  • •Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens.
  • •Programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting).
Experience:10+ yearsSemiconductorsHBMDRAMSoCMemory-centric designsAI/ML workloads
Education:
Skills:Root-cause analysisDebuggingCross-functional collaborationTechnical documentationDesign review participation
Tech Stack:SystemVerilogVerilogRTL-to-GDSSynthesisStatic timing analysisCadenceSynopsysSiemensPythonTCLPerlShell scriptingRTLGDSClockingResetPower intentConfiguration infrastructureDFTScan

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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