Senior Engineer, STPG PE (FDV-Verilog)

Build scalable, reusable Verilog test-program frameworks for NAND functional and design validation, covering deterministic flows and pseudo-random validation (RSG). Execute simulation-based test development, automated execution improvements, and deep failure analysis (digital and analog) to drive root-cause identification and timely cross-functional issue closure. Use data-driven dashboards and AI/ML-assisted techniques (triage, anomaly detection, coverage gap identification) to increase test efficiency, coverage, and debug productivity across products and technology nodes.