Senior Physical Design Engineer - Neuromorphic Computing

Intel
Santa Clara
Workplace: HybridFull timeUSD 164,470 - 269,100 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Hands-on","Problem-solving","Collaboration"]

Drive physical design for Intel’s neuromorphic computing platform, transforming event-driven chip breakthroughs into real-world physical AI systems. You’ll engineer chiplet and advanced packaging integration, architect floorplans, and lead block- and chip-level closure to meet performance, power, and area targets. Work with RTL designers through synthesis/place-and-route trials, resolve timing and physical signoff issues, and iterate using VCS+SDF simulations and custom tool scripts.

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FursaFursa
Intel
Intel
2 days ago

Senior Physical Design Engineer - Neuromorphic Computing

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Source: Company careers pageValidated by: Fursa AI
Last checked: 17 hours agoStatus: Live

Job Summary

Drive physical design for Intel’s neuromorphic computing platform, transforming event-driven chip breakthroughs into real-world physical AI systems. You’ll engineer chiplet and advanced packaging integration, architect floorplans, and lead block- and chip-level closure to meet performance, power, and area targets. Work with RTL designers through synthesis/place-and-route trials, resolve timing and physical signoff issues, and iterate using VCS+SDF simulations and custom tool scripts.
Location: Santa Clara
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Understand system specifications to derive package and die-level requirements.
  • •Architect full-chip floorplans and coordinate partition-level floorplans with macro/pin placements and keep-outs.
  • •Partner with RTL designers to define timing constraints, run synthesis and place-and-route trials, and resolve timing, EM/IR, LVS, and DRC violations.
  • •Run back-annotated VCS+SDF simulations and provide feedback to designers to meet power/performance targets.
  • •Write custom scripts and define tool flows to drive low-power/high-performance custom design execution.

Pay and Benefits

Salary: USD 164,470 - 269,100 annually
Equity and Bonus:Equity
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •Bachelors with 6+ years or Masters with 4+ years of hands-on physical design experience delivering multiple silicon tape-outs.
  • •6+ years setting up floorplans, defining timing/power constraints, and iterating through synthesis and place-and-route to meet product KPIs.
  • •6+ years of experience with scripting languages such as Perl, TCL, and Python for physical design tool workflows.
  • •4+ years debugging FEV and RV reports and planning ECOs.
  • •2+ years of experience with chiplet integration and/or advanced packaging.
Experience:SemiconductorsAINeuromorphic computingEDA
Education:Bachelor's
Skills:Hands-onProblem-solvingCollaboration
Tech Stack:PerlTCLPythonCadence (Virtuoso)Synopsys (Fusion Compiler)PrimetimeStarRCSiliconSmartVCSSDFJavaC++FEVRVECOEM/IRLVSDRCUCIeSerDes

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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