SoC Digital Design Engineer, Multimedia Lab

ByteDance
Singapore
Workplace: OnsiteFull timeFunction: Creative Production (Video/Audio/Photo)Experience: 3+ yearsEducation: bachelorsSkills: ["Technical excellence","Cross-functional collaboration"]

Build and scale video codec hardware solutions by designing SoC top-level or subsystem architectures for NoC/CPU/NPU/ISP/Codec. Implement RTL in Verilog/SystemVerilog, run lint and clock/reset domain crossing checks, and collaborate across verification and backend teams to drive coverage closure, synthesis, SDC generation, STA, and power optimization. Contribute to low-power strategies using clock/power gating and the UPF flow for advanced process-node tape-outs.

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FursaFursa
ByteDance
ByteDance
1 month ago

SoC Digital Design Engineer, Multimedia Lab

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 30 days agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Build and scale video codec hardware solutions by designing SoC top-level or subsystem architectures for NoC/CPU/NPU/ISP/Codec. Implement RTL in Verilog/SystemVerilog, run lint and clock/reset domain crossing checks, and collaborate across verification and backend teams to drive coverage closure, synthesis, SDC generation, STA, and power optimization. Contribute to low-power strategies using clock/power gating and the UPF flow for advanced process-node tape-outs.
Location: Singapore
Workplace: Onsite
Employment Type: Full time
Job Function: Creative Production (Video/Audio/Photo)
Seniority: Mid level

Key Responsibilities

  • •Participate in defining SoC top or subsystem architecture (NoC/CPU/NPU/ISP/Codec) and conduct PPA evaluation early in design.
  • •Write high-quality RTL (Verilog/SystemVerilog) and maintain design documentation.
  • •Run front-end quality control checks including lint, CDC, and RDC to ensure standards compliance.
  • •Collaborate with verification to debug and close coverage; support synthesis, SDC generation, STA, and power optimization with backend/mid-end teams.
  • •Contribute to low-power chip strategy using clock gating and power gating and support UPF flow.

Key Requirements

  • •Bachelor’s degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field.
  • •3+ years of experience in digital front-end design.
  • •Strong Verilog/SystemVerilog skills and a solid foundation in digital circuits.
  • •Experience with front-end EDA tools such as Spyglass, Design Compiler, and PrimeTime.
  • •Fluency in at least one scripting language (Python, Perl, Tcl, or Makefile) for automation.
Experience:3+ yearsSoCDigital front-end designVideo codecsFPGAASIC
Education:Bachelor's
Skills:Technical excellenceCross-functional collaboration
Tech Stack:SoCVideo codecFPGAASICRTLVerilogSystemVerilogSpyglassDesign CompilerPrimeTimePythonPerlTclMakefileNoCCPUNPUISPCodecPPA

Company Brief

ByteDance
Develops consumer internet and content platforms, including TikTok and other apps for short-form video, news, and entertainment. It also builds advertising, commerce, and creator tools that connect audiences, brands, and publishers across global markets.
Industry: Digital Media
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Established Company
Headquarters: Beijing, China
Founded: 2012
WebsiteLinkedIn