SMTS, Design Rule Enablement Team TPG

Micron Technology
Japan
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 15+ yearsEducation: mastersSkills: ["Cross-functional collaboration","Problem-solving","Technical communication","Documentation improvement","Technical issue resolution"]

Lead design enablement for DRAM technologies by developing and refining design rules, requirements, and test structures across all DRAM generations. Define project and sub-milestones within layout schedules, manage design rule checks and deviation responses, and partner with cross-functional teams to optimize PPAC (performance, power, area, cost). Drive evaluation of test structures for next-gen devices, address process-window vs. die-size issues, and improve R&D documentation and APR workflows using AI/GenAI for efficiency.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Micron Technology
Micron Technology
4 weeks ago

SMTS, Design Rule Enablement Team TPG

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 18 hours agoStatus: Live

Job Summary

Lead design enablement for DRAM technologies by developing and refining design rules, requirements, and test structures across all DRAM generations. Define project and sub-milestones within layout schedules, manage design rule checks and deviation responses, and partner with cross-functional teams to optimize PPAC (performance, power, area, cost). Drive evaluation of test structures for next-gen devices, address process-window vs. die-size issues, and improve R&D documentation and APR workflows using AI/GenAI for efficiency.
Location: Japan
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Lead efforts to develop and refine design rules, requirements, and test structures for all DRAM generations and associated advanced CMOS.
  • •Define milestones and sub-milestones within layout schedules and ensure timely execution across teams.
  • •Partner with Design, Product Engineering, Process Integration, Business Units, and Quality to optimize PPAC (performance, power, area, cost) for Micron DRAM products.
  • •Manage test structure evaluation to support next-gen device development and quantify process margins.
  • •Ensure robust design rule checks and appropriate responses to deviations, addressing process-window vs. die-size issues and driving cross-node design rule alignment.

Key Requirements

  • •MS/PhD in Electrical Engineering, Microelectronics, Physics, or a related field.
  • •15+ years of semiconductor industry experience across Process Integration, PDK development, Yield Enhancement, Product Engineering, and design/test structure development.
  • •Strong understanding of semiconductor process flow and key DRAM/advanced CMOS components.
  • •Experience with test structure design and characterization.
  • •Familiarity with Cadence & Siemens tools and the ability to perform layout tasks.
Experience:15+ yearsSemiconductorDRAMPDK developmentYield enhancementProcess integration
Education:Master's in Electrical Engineering, Microelectronics, Physics
Skills:Cross-functional collaborationProblem-solvingTechnical communicationDocumentation improvementTechnical issue resolution
Tech Stack:CadenceSiemensAPR workflowsAILLMsGenAIAdvanced Mask DesignScribe & FrameLayout & Design Document

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
Glassdoor
Glassdoor: 3.7
WebsiteLinkedIn