Senior ASIC Design Efficiency Engineer
Santa Clara, Austin, Durham
Workplace: OnsiteFull timeUSD 196,000 - 310,500Function: Design (Product/UX/UI/Visual)Experience: 12+ yearsEducation: bachelorsSkills: ["Interpersonal skills","Collaboration","Communication","Work effectively in a diverse team"]Develop ASIC design efficiency methods for hardware accelerators and processors across mobile, embedded, and datacenter platforms. Improve performance, power, and area (PPA) through RTL implementation, verified design delivery, and methodology/infrastructure development. Collaborate with architecture, design, verification, and VLSI teams to craft high-performing GPUs, while applying strong logic design and computer architecture fundamentals.
