NVIDIA

3 months ago

Senior ASIC Timing Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 16 hours agoStatus: Live

Job Summary

Lead timing analysis and closure for NVIDIA GPUs, CPUs, LPUs, and SoCs across blocks, clusters and full chip levels. Collaborate with RTL, DFX, clocks and other teams to devise timing strategies, constraints, and ECOs; drive timing and power convergence; improve timing convergence flows with methodology teams; contribute to cutting-edge AI/compute projects.

Location: Santa Clara, Austin, Durham

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level
•Collaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs
•Contribute to Cutting-Edge Projects: Play a pivotal role in the success of our innovative projects and advancement of our technology. Leverage your expertise to improve timing convergence flows in collaboration with methodology teams

Pay and Benefits

Salary: USD 136,000 - 218,500 annually

Equity and Bonus:Equity

Perks:EquityHealth Insurance

Key Requirements

•BS (or equivalent experience) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent experience) with 3 years’ experience in Timing and STA
•Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management
•Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
•Experience in physical design and optimization e.g., synthesis, placement, routing, logic restructuring, etc. to improve timing and power
•Expertise and in-depth knowledge of industry standard STA and timing convergence tools

Experience:SemiconductorsASICGPUAI hardware

Education:Bachelor's

Skills:CommunicationCollaborationProblem-solving

Tech Stack:Static Timing AnalysisECOsDFTSynthesisPlacementRouting

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

3 months ago

Senior ASIC Timing Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 16 hours agoStatus: Live

Job Summary

Location: Santa Clara, Austin, Durham

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level
•Collaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs
•Contribute to Cutting-Edge Projects: Play a pivotal role in the success of our innovative projects and advancement of our technology. Leverage your expertise to improve timing convergence flows in collaboration with methodology teams

Pay and Benefits

Salary: USD 136,000 - 218,500 annually

Equity and Bonus:Equity

Perks:EquityHealth Insurance

Key Requirements

•BS (or equivalent experience) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent experience) with 3 years’ experience in Timing and STA
•Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management
•Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
•Experience in physical design and optimization e.g., synthesis, placement, routing, logic restructuring, etc. to improve timing and power
•Expertise and in-depth knowledge of industry standard STA and timing convergence tools

Experience:SemiconductorsASICGPUAI hardware

Education:Bachelor's

Skills:CommunicationCollaborationProblem-solving

Tech Stack:Static Timing AnalysisECOsDFTSynthesisPlacementRouting

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor