Lead RTL/FPGA Design Engineer

Own end-to-end RTL development for a high-performance coherent modem for free space optical (FSO) communications on the Aalyria Space team. Translate DSP algorithms into clean, synthesizable VHDL/SystemVerilog, lead micro-architecture for key DSP blocks, integrate FEC engines and high-speed interfaces, and drive verification, debug, and static timing closure through silicon bring-up. Partner closely with DSP algorithm developers and system architects and support hardware/software integration and bench testing.