Senior Software Architect

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 210,000 - 390,000 annuallyFunction: Software EngineeringExperience: 10+ yearsEducation: mastersSkills: ["Collaboration","Technical excellence","Continuous learning","Leadership","Code review","Performance optimization","Deep-dive analysis","Adaptability"]

Architect and evolve the Xcelium RTL/logic simulator for next-generation hardware verification, focusing on RTL/logic simulation scaling and Timing Constraints Verification inside the simulator. You’ll enhance SDC constraint support using graph algorithms, perform bottleneck analysis, and deliver C/C++ performance optimizations to improve compilation speed and memory footprint. Lead junior engineers, collaborate in a distributed team, and write specifications and unit tests.

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Cadence Design Systems
Cadence Design Systems
10 hours ago

Senior Software Architect

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Source: Company careers pageValidated by: Fursa AI
Last checked: 10 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Architect and evolve the Xcelium RTL/logic simulator for next-generation hardware verification, focusing on RTL/logic simulation scaling and Timing Constraints Verification inside the simulator. You’ll enhance SDC constraint support using graph algorithms, perform bottleneck analysis, and deliver C/C++ performance optimizations to improve compilation speed and memory footprint. Lead junior engineers, collaborate in a distributed team, and write specifications and unit tests.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Mid level

Key Responsibilities

  • •Enhance and support the Xcelium RTL/logic simulator engine by adding new features and extending existing features.
  • •Enhance and support Timing Constraints Verification technology used inside the Xcelium simulator.
  • •Design, tune, and innovate graph algorithms involving SDC constraints support on multi-billion-node graphs.
  • •Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.
  • •Lead junior engineers and collaborate with global team members to deliver high-quality results in a distributed environment; contribute to technical discussions, code reviews, specifications, and unit tests.

Pay and Benefits

Salary: USD 210,000 - 390,000 annually
Equity and Bonus:Equity
Perks:Paid LeavePaid Holidays401kMedicalDentalVisionEquity

Key Requirements

  • •MS in Computer Science or Electrical Engineering with a minimum of 12 years of experience, or PhD with a minimum of 10 years of experience.
  • •10+ years of experience in EDA software development.
  • •Strong background in RTL/logic simulation, SDC constraints, and Timing Analysis (including path exceptions handling in a STA tool).
  • •Excellent programming skills in C/C++ and deep understanding of SystemVerilog or Verilog.
  • •Experience in multi-threaded/concurrent programming (prior RTL/logic simulation software development is a plus).
Experience:10+ yearsEDARTL/logic simulationSemiconductorHardware verificationGraph algorithmsPerformance optimization
Education:Master's
Skills:CollaborationTechnical excellenceContinuous learningLeadershipCode reviewPerformance optimizationDeep-dive analysisAdaptability
Tech Stack:C++CSystemVerilogVerilogSDCSTARTL/logic simulationGraph algorithmsMulti-threaded programming

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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