Principal Product Validation Engineer

Cadence Design Systems
Noida
Workplace: OnsiteFull timeFunction: Communications, PR & CommunityEducation: bachelorsSkills: []

Lead functional verification and validation of complex digital systems (SoC) using HDL-based languages and SystemVerilog-based environments. Design, implement, and debug verification environments and EDA tool flows to ensure robust hardware design verification, with scripting for process automation and exposure to PCIe/USB/DP protocols for added context.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
7 months ago

Principal Product Validation Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live

Job Summary

Lead functional verification and validation of complex digital systems (SoC) using HDL-based languages and SystemVerilog-based environments. Design, implement, and debug verification environments and EDA tool flows to ensure robust hardware design verification, with scripting for process automation and exposure to PCIe/USB/DP protocols for added context.
Location: Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community

Key Responsibilities

  • •Debug design/ verification problems using HDL-based languages and EDA tools; contribute to verification planning and debugging strategies.
  • •Design and implement complex functional verification environments for SoC verification using SystemVerilog/UVM.
  • •Execute and automate verification tasks, including scripting for process automation and testBench orchestration.
  • •Perform functional verification of complex digital systems, using HVL like SystemVerilog to validate architectures and protocols.
  • •Collaborate on verification strategies and leverage knowledge of PCIe, USB3/4, and DP with added context.

Key Requirements

  • •Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/or VHDL).
  • •Prior experience in simulation/emulation using these languages with good working knowledge of EDA tools (Cadence/Others) focused on debugging design/verification problems.
  • •Experience in process automation with scripting.
  • •Experience with SystemVerilog, C++, UVM.
  • •Experience with Functional Verification of complex digital systems (SoC Verification) with a Hardware Verification Language (HVL) like SystemVerilog.
Experience:SemiconductorEDAHardware verification
Education:Bachelor's
Tech Stack:VerilogVHDLSystemVerilogC++UVMHDLE DA toolsCadence

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor