Senior SoC Digital Design Engineer, Multimedia Lab

Design and implement SoC subsystems for high-efficiency video encoding and processing hardware. You’ll help define SoC architecture, write RTL in Verilog/SystemVerilog, run front-end quality checks (Lint, CDC/RDC), and collaborate with verification and backend teams on coverage closure, synthesis, SDC/STA, and power optimization. Support low-power strategies using clock/power gating and the UPF flow, leveraging EDA tools and scripting for automation.