Principal Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 9+ yearsEducation: bachelorsSkills: ["Mentoring","Communication","Teamwork","Problem-solving"]

Principal Design Engineer responsible for DFT ownership across projects, driving test architecture, RTL changes for DFT, boundary scan and iJTAG implementations, and collaboration with cross-functional teams to deliver high-speed, low-power designs while mentoring junior engineers.

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Cadence Design Systems
Cadence Design Systems
6 months ago

Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live

Job Summary

Principal Design Engineer responsible for DFT ownership across projects, driving test architecture, RTL changes for DFT, boundary scan and iJTAG implementations, and collaboration with cross-functional teams to deliver high-speed, low-power designs while mentoring junior engineers.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Own DFT for projects, including defining test architecture and RTL changes for DFT.
  • •Performing scan insertion, LEC checks, low power CLP checks.
  • •Develop timing constraints for test mode timing closure; scan and ATPG for different fault models.
  • •Boundary scan, ACJTAG, IEEE 1500 implementation and verification; IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests; run zero delay and timing simulations and debugging.
  • •Interact with customers on DFT aspects and support Marketing & Pre-Sales; mentor junior engineers and drive innovation/automation.

Key Requirements

  • •BE/B.Tech/M.E/M.Tech with 9+ years of relevant work experience and strong understanding of DFT concepts.
  • •Strong hands-on experience using industry standard EDA Tools.
  • •Experience with logic simulators from one or more EDA vendors.
  • •Experience on industry standard ATPG tools like Cadence Modus.
  • •Experience with RTL lint tools like Jasper.
Experience:9+ yearsSemiconductorEDAHardware design
Education:Bachelor's
Skills:MentoringCommunicationTeamworkProblem-solving
Tech Stack:DFTEDA ToolsCadence ModusJasperPerlPythonTclRTL2GDSSynthesisSTAIR drop

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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