Senior SoC Subsystem and I/O Architect - LPU

NVIDIA
United States
Workplace: RemoteFull timeUSD 184,000 - 356,500 annuallyFunction: Solutions Engineering & Sales EngineeringExperience: 8+ yearsEducation: mastersSkills: ["Communication","Problem-solving","Collaboration","Leadership"]

Define high-level SoC subsystem architecture for LPU products and translate product requirements into architectural specifications for uncore, IO, memory, and firmware interfaces. Collaborate with IP teams to produce detailed build documents for PCIe/CXL, NVLink, UCIe, AXI/CHI and NoC fabrics. Build/guide architectural models in C++/SystemC/Python to validate architecture before RTL silicon. Drive tradeoffs across bandwidth, latency, power, area, and reliability.

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FursaFursa
NVIDIA
NVIDIA
2 months ago

Senior SoC Subsystem and I/O Architect - LPU

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 14 hours agoStatus: Live

Job Summary

Define high-level SoC subsystem architecture for LPU products and translate product requirements into architectural specifications for uncore, IO, memory, and firmware interfaces. Collaborate with IP teams to produce detailed build documents for PCIe/CXL, NVLink, UCIe, AXI/CHI and NoC fabrics. Build/guide architectural models in C++/SystemC/Python to validate architecture before RTL silicon. Drive tradeoffs across bandwidth, latency, power, area, and reliability.
Location: United States
Workplace: Remote
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Define high-level SoC subsystem architecture for LPU products.
  • •Convert LPU product requirements into architectural specifications for uncore, IO, memory, firmware-facing, boot, reset, safety, fault tolerance, diagnostic, and power regulation subsystems.
  • •Collaborate intimately with IP teams to develop detailed build documents for PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, NoC fabrics, memory controllers, coherency blocks, MMUs/IOMMUs, boot, reset, and associated SoC infrastructure.
  • •Specify subsystem behavior encompassing enumeration, capability discovery, configuration flows, sequence control of memory operations, data consistency, address mapping, interrupt handling, virtualization, error handling, and firmware/software-visible controls.
  • •Build or guide functional and architectural models from specifications, using C++, SystemC, Python, or similar languages.

Pay and Benefits

Salary: USD 184,000 - 356,500 annually
Equity and Bonus:Equity
Perks:Equity

Key Requirements

  • •BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
  • •8+ years of proven experience in SoC architecture, subsystem architecture, IO architecture, interconnect architecture, GPU/CPU architecture, accelerator architecture, or high-performance systems.
  • •Strong understanding of SoC architecture and uncore subsystem development.
  • •Extensive understanding of IO and interconnect cores including PCIe, CXL, NVLink, NVLink-C2C, UCIe, AXI, CHI, or NoC fabrics.
  • •Experience crafting functional models, architectural models, golden models, or C/SystemC models from architecture specifications.
Experience:8+ yearsSoCGPUAIHardwareSemiconductor
Education:Master's
Skills:CommunicationProblem-solvingCollaborationLeadership
Tech Stack:PCIeCXLNVLinkNVLink-C2CUCIeAXICHINoCSystemCC++PythonMemory controllersMMUsIOMMUsBootResetFirmware

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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